Optimum Decoupling of Digital ICs

Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.
47uF might rank somewhere between the two sizes that you tried.

47uF might rank somewhere between the two sizes that you tried.

I am using AD1865N-K. This dac requires a lot less current than the TDA1543. A capacitor as large as 100uF may not be required- I should not need that much charge 'on tap' if I am drawing less current with my Cmos logic.
 
This is all interesting stuff.
Peter,
you are using these BG caps in parallel with small value
ceramic if I remember correctly? [Sorry I did not re-read the thread in it,s entirety before posting this]


Ferrite beads, these are connected in series post regulation, yes?
Are they likely to introduce problems of their own?
I have no scope as yet [I know..silly, but well:xeye: ] and wish
to play as safe as possible when flying blind so to speak:dodgy: .

Another matter,
I am working on the p2p layout at the moment.
I am trying to keep 'traces' as short as possible and also aiming for a compact unit.
Is is it OK to run traces over or under the 8412 ?
I am also trying to avoid supply lines crossing signal, wise? or
unnecessary?



Setmenu:clown:
 
The best decoupling is to use the BG or OSCON paralleled with .01uf CKO5, or X7R 50volt types ceramic. All Electrolytic even the BG's caps become inductor at high frequency, however there low frequency performance is great. So you then use the ceramic which work well at high frequencies, this will cover the range of frequencies where the BG or OSCON's stop working.

If you doing point to point wiring the grounds will become very important. Try to find some 3M copper foil tape to use for GND. Keep it as wide as possible then connect each chip ground to that foil. Do the same for the power it will keep the impedances low and that what you want for power and ground.

The ground for analog must be complete isolated from the digital ground. The all ground should meet in a star point on the chassis.

As for wire runs just be careful on long runs and high impedance run. You should not have any long that are parallel with other runs. It OK to cross another wire diagonally. The analog runs and the 8412 receiver and adjustable regulators or the most sensitive.
 
Pedija,

These are the standards for grounding mixed signals devices. If you read some of the Analog Devices or Burr Brown applications notes you can find this out for your self. Of course you are welcome to tell us how you would implement a grounding systems for a converter. Our would you daisy chain all the grounds together.

Please Advise
:xeye:
 
Do we really need ceramics?

I have read a lot of threads suggesting avoiding the use of ceramics in parallel with BGs/Oscons.

Given 2nH inductance per cm of PCB trace and about 2cm of decoupling trace per 14pin DIL package, at 10Mhz we get...

Zi=2*3.14*(10*10^6)*2*(2*10^-9) = 0.251 Ohms

Overall the impedance is given by (R^2 + (Zi - Zc)^2)^0.5

Zc is very small
Zi dominates as long as R remains small (check out an OsCon at 10Mhz)

My point is lead inductance dominates anyway, regardless of the type of capacitor (as long is it is fairly good).
 
It is normal to bypass with a ceramic cap and that it. If you use a small BG or OSCON it will get close working at 10Mhz. However, it will not hurt the performance to use a ceramic with it. Of course doing the point-to-point layout can have some disadvantages as for as grounding and node impedances.

But hay don't take my would for it go build it. Do some engineering, however you'll need a scope. You might look on EBAY for a good deal on one.

Cheers
 
jewilson said:
Pedija,

These are the standards for grounding mixed signals devices. If you read some of the Analog Devices or Burr Brown applications notes you can find this out for your self. Of course you are welcome to tell us how you would implement a grounding systems for a converter. Our would you daisy chain all the grounds together.

Please Advise
:xeye:
Jim,

Yes, I am aware of what is recommended in some Analog’s articles (for instance in the “Grounding in High Speed Systems“ by Walt Kester and James Bryant). However, there are some reasons why the voltage difference between the two grounds of the one chip, and which can appear in this case, is bad.

http://www.sigcon.com/Pubs/edn/adcgrounding.htm
http://www.sigcon.com/Pubs/edn/multipleadc.htm

As about what would I do – yes, I would do something like what is suggested by Howard Johnson and I certainly would not daisy chain all the grounds. However, there is no problem in daisy chaining of the “cousin” grounds. In fact, it is not what I would do but what I actually do and you can find the info about it on my site, check the TDA1541A DAC page, schematics are also drawn to show the ground routing as much as possible.

Pedja
 
Pedja,

This application note states

In higher resolution systems requiring more noise isolation, you begin to worry about noise induced by stray digital currents flowing across the analog ground region of your pc board. To prevent these currents, you may choose to divide your pc ground into two regions—an analog region and a digital region—connected at one common point directly under the ADC. The common connection must be short and fat enough so that little voltage difference appears between the DGND and AGND pins of the ADC.

That is what I was saying. The standard is a star ground with connected planes where circulating ground currents or canceled. I have also found from experience that these grounds can be connected in a centralized location close to the power supply
commands or grounds.
 
Hi All
Time for a reality check before I go any further.

As I seem to be about to undertake this project without a scope:whazzat:

I would guess that this is a bad idea:nod:

And there I was naively day dreaming about making something
without the correct tools...

£££££.....Sigh

I think this little project is going to have to go on hold for a while:( :(



Setmenu:xeye: :clown:
 
Can anyone with fresh eyes look at post #220?

Can anyone with fresh eyes look at post #220?

I continue to remain unsure about:

1) The use of ferrites in op-amp supply lines- is it sonic disaster or a good idea? Anyone tried it?

2) The use of small 0.1uF bypass caps with digital logic when a ferrite is in use. Will such a small value of capacitor be able to meet the supply demand of the IC? Will the ferrite act as a high impedance and the capacitor will run out of 'juice'?

:confused:
 
Confused...

Thanks Jocko, but I am getting confused! :bawling:

Are you suggesting a CLC filter?

or

to stick with an LC filter and replace the 0.1uF (ceramic) decoupling capacitor with a larger HF electrolytic (e.g. 47uF BG NX-Hiq)

(My problem with the first option is that there is no damping to prevent many electrolytics serving ICs throughout the board from resonating together - they will all be in parallel.)




BTW. Approve of the new Avatar. Must do one for myself.
 
Re: Do we really need ceramics?

Oli said:
I have read a lot of threads suggesting avoiding the use of ceramics in parallel with BGs/Oscons.

Given 2nH inductance per cm of PCB trace and about 2cm of decoupling trace per 14pin DIL package, at 10Mhz we get...

Zi=2*3.14*(10*10^6)*2*(2*10^-9) = 0.251 Ohms

Overall the impedance is given by (R^2 + (Zi - Zc)^2)^0.5

Zc is very small
Zi dominates as long as R remains small (check out an OsCon at 10Mhz)

My point is lead inductance dominates anyway, regardless of the type of capacitor (as long is it is fairly good).


Hi Oli,

Point well made !

and it is worse, as inductance is about 1 nH/mm for conductors having their counterpart current far away. On a 1.6 mm double layer board where both currents run on one side, it reduces to 0.5nH/mm.

cheers
 
Oli:

At low frequencies, a ferrite has minimal inductance, and it decreases with frequency. At the higher frequencies........maybe 5 MHz for a 73 mix, or 20 MHz for a 43 mix, the ferrite acts as a resistor, absorbing energy. The resistance for a 1/2 turn "bead on a lead" type will probably be around 10-30 ohms over its useful range. (Around 30 MHz for the 73 mix, and about 100 MHz for the 43 mix.)

I may have accidentally refered to you as "Oil", but I am not certain. Sorry about that...........

Jocko
 
Cheers Guido

Cheers for your reply Guido- It has taken a lot of time for me to adjust my view on decoupling!

I had no idea that inductance could be as poor as 1nH/ millimetre ! (for distance traces)

In my previous example the impedance of the trace could lie somewhere between the aforementioned 0.251Ohm and 2.51Ohm- very high compared with a half-decent electrolytic!


Ceramics seem pointless :smash:
 
Unfortunately you still have not answered my question

Jocko,

You have convinced me that-

1) Ferrites are 'invisible' at low frequencies
2) Ferrites behave like resistors at high frequencies

:)

Unfortunately you still have not answered my question.

:confused:

Which arrangement of supply do you suggest:

1) Electrolytic + Ferrite + Decoupling capacitor (CLC)

or

2) Ferrite + Large decoupling capacitor (LC)

(Guido's ideas are steering me towards LC filtering, with a 47uF HF electrolytic near to each IC.)
 
Oli,

If ceramic were useless no one would use them on high-speed designs. If people did use ceramics for decouple on high-speed design that market would almost dry up for them. I found many digital systems that would not pass EMI tests with out multiple decoupling caps and that a fact.
:yes:

The best thing for you to do is build this buy all these decoupling and filter dodads then test it for yourself. That the best way to learn.:smash:
 
There isn't an answer for all applications. It depends on speed and di/dt of the IC, how far the IC is away from the big 'lytic, and well......just stuff in general.

I do not see the harm in placing a small......say 4.7 or 10 uF 'lytic at each IC, assuming that the total C combined with the big one at the regulator is not so high as to make the regulator go wack-o. Some regulator/cap combos will do that. Which is why you will see some guys here put a small (say 0.47 ohm) resistor in series with the cap.

So......I would try Big C-ferrite-small C/bypass arrangement as a starting point. Try it and see........that is how we all started.

And yes....we screwed up and learned from it. We even screw up now sometimes. We just get better at hiding our screwups.

Jocko
 
Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.