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Old 17th September 2011, 04:11 PM   #191
Calvin is offline Calvin  Germany
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Location: close to Basel
Hi,

right Kirchhoffs law applies, but a cap doesn´t conduct at DC. Only the AC signal current ´passes´ the caps and generates a signal voltage over Riv The trimming is done without signal under DC-conditions.
The 560Kohm resistors shown in the earlier sketches supply for a dc-current-path though and a positive dc-offset voltage over Riv occurs.
The Input of the stage will also be pulled into positive direction and eventually the protection diodes of the DAC will start conduction, thereby limiting the offset at the input to the Vf of the diodes. The positive potential of the supply voltage will be approx. the supply voltage, the negative supply potential will be at approx. Vf.
The bipolar version is more forgiving in this respect and creates lower offsets from the start. Anyway, the variations in the symmetry of the supply line potentials are the most sensitive indicator for trimming.

jauu
Calvin
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Old 17th September 2011, 04:18 PM   #192
EUVL is offline EUVL  Europe
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> Anyway, the variations in the symmetry of the supply line potentials are the most sensitive indicator for trimming.

We agree on that.
It is also why I mentioned in post #170 to trim offline using a multimeter first before fine trimming in circuit.

Also for trimming one might lower the 560k resistors to 2k temporary, and remove them once done.

Patrick
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Old 17th September 2011, 06:36 PM   #193
Alexium is offline Alexium  Ukraine
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Quote:
Originally Posted by EUVL View Post
I have been asked to publish a schematics of SEN in combination with the likes of ES9018, PCM1794, 1798, etc., as descrived in post #170.

Here you are. Hope this makes it clear.
Thanks!
It looks like the very same Sen, only with a current bias circuit. Does it mean one can use Cen the same way?
I don't quite understand how to power this constant current source properly. How separate must it be? Is it possible to use the same power supply that powers I/V?
BTW, what is the acceptable voltage range for I/V? 18V isn't too practical, 15V or even 12V would be better...

Last edited by Alexium; 17th September 2011 at 06:42 PM.
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Old 17th September 2011, 07:01 PM   #194
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Patrick,
Your Zen IV link shows that the offset voltage can just be derived from a potential divider from the power rails. Are you suggesting that its possible to do this with SEN/CEN? It would certainly be less trouble than another CCS and -ve supply.
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Old 17th September 2011, 07:19 PM   #195
EUVL is offline EUVL  Europe
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> It looks like the very same Sen, only with a current bias circuit. Does it mean one can use Cen the same way?

Yes, but you probably might want to try using 2 pairs of JFETs instead of 1.

> I don't quite understand how to power this constant current source properly.
> How separate must it be?

Totally separate, as drawn. i.e. Separate battery required.

> Is it possible to use the same power supply that powers I/V?

Not for SEN / CEN.


Patrick

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Last edited by EUVL; 17th September 2011 at 07:22 PM.
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Old 17th September 2011, 07:21 PM   #196
EUVL is offline EUVL  Europe
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> Are you suggesting that its possible to do this with SEN/CEN?

Absolutely NOT.
SEN / CEN have floating supplies that swing with the output signal.

But you can think of a way to use e.g. the analog supply of the DAC and some additional circuit to provide that voltage.


Patrick
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Old 17th September 2011, 08:03 PM   #197
EUVL is offline EUVL  Europe
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Note that the schematics posted in post #182 only applies to ES9018 when use in stereo mode.

If you want to use ES9018 as 4 or 8 channel, I think it is wise to apply voltage offset (Vcc/2, or 1.65V for 3.3V supply).
As mentioned above, this is best taken off the analog supply of the DAC.
In that case (4 or 8 channel), the normal SEN / CEN circuit applies.
No need to increase no of FETs or Idss.

You may (ideally but not necessarily) wish to keep Vds of both top & bottom JFETs identical when applying this offset voltage to the JFET gates.
In that case, you should change R1 & R2 such that

R1 / R2 = (18V/2 + 1.65V) / (18V/2 - 1.65V) = 1.45

Keeping R1 at 560k, R2 should be changed to 390k.


Patrick

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Last edited by EUVL; 17th September 2011 at 08:30 PM.
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Old 17th September 2011, 08:08 PM   #198
Alexium is offline Alexium  Ukraine
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Quote:
Originally Posted by EUVL View Post
Totally separate, as drawn. i.e. Separate battery required.
Understood.
What about the Sen/Cen power voltage? How far can I lower it without considerable loss in characteristics?
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Old 17th September 2011, 08:11 PM   #199
EUVL is offline EUVL  Europe
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> BTW, what is the acceptable voltage range for I/V? 18V isn't too practical, 15V or even 12V would be better...

Minimum 15.6V (min 5V Vds for each FET plus 5.6v pk-pk swing), maximum 25V (limited by Vgds of 2SJ74).
For SEN, you might go further to 36V if you so wish.

If you lower it further, you increase distortion significantly due to non-linear JFET capacitances at low Vds.
The higher the voltage, the lower the capacitances, the lower the distortion.


Patrick

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Last edited by EUVL; 17th September 2011 at 08:14 PM.
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Old 18th September 2011, 08:07 AM   #200
EUVL is offline EUVL  Europe
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Seems that there are quite a few 9018 owners out there not entirely happy with their own IVs.

As requested attached a schematics for the 9018 operating in Voffset mode.
Shown here as used for 4 or 8 channels.
For stereo double the number of JFETs (in case of SEN use 4x 2SK369 as posted in #182.


Disclaimer :
I have not built this, nor do I intend to in the coming months.


Patrick
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