Something like this :
PEAKTECH 3725 - 3 -stelliger Multi-Funktionstester - Multimeter, digital bei reichelt elektronik
There are cheaper ones.
Just look for DMM with hfe or transistor test.
Patrick
PEAKTECH 3725 - 3 -stelliger Multi-Funktionstester - Multimeter, digital bei reichelt elektronik
There are cheaper ones.
Just look for DMM with hfe or transistor test.
Patrick
Not to beat this offset current source thing to death, but it occurs that one could use the ground sense terminal "GNDS" of the MAX6162 and connect it to the input of the I-V. Then merely a resistor between there and the connection of OUTF and OUTS, with the current given simply by Vref/R. According to theory, as long as the ground sense pin stays no more that +/- 300mV above or below GND (which would be tied to system common) the current will be regulated. Maxim is notably silent about the quality of the sense inputs, so your mileage may vary. But this would work better the lower the input Z of the I-V.
Not nearly that bad (although I would use other topologies with considerably lower noise). Suppose we use the 5.00V part, thus a 2.00k resistor in series. Integrating over a 20kHz BW I get about 20uV rms for the voltage. Dividing by 2k gives about 10nA rms. Against the half-scale 2mA of the DAC under consideration, we have about 106dB from that specific contribution. And that's a noise consideration, but roughly would be dithering below an LSB of 17 bits. Not great, not horrible. On my third glass of wine here so please someone corroborate 
(edit) Having said that, you did say the 1704. I was addressing the problem of the other DAC which needs a positive current injected to center at the 2.00mA half-scale.
As far as current sources/sinks go, many will allow substantial filtering of the reference voltage that determines the current. Definitely a good thing to do, but at sufficiently low frequencies eventually the "1/f" component will render filtering otiose.
(edit) Having said that, you did say the 1704. I was addressing the problem of the other DAC which needs a positive current injected to center at the 2.00mA half-scale.
As far as current sources/sinks go, many will allow substantial filtering of the reference voltage that determines the current. Definitely a good thing to do, but at sufficiently low frequencies eventually the "1/f" component will render filtering otiose.
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Not nearly that bad (although I would use other topologies with considerably lower noise). Suppose we use the 5.00V part, thus a 2.00k resistor in series. Integrating over a 20kHz BW I get about 20uV rms for the voltage. Dividing by 2k gives about 10nA rms. Against the half-scale 2mA of the DAC under consideration, we have about 106dB from that specific contribution. And that's a noise consideration, but roughly would be dithering below an LSB of 17 bits. Not great, not horrible. On my third glass of wine here so please someone corroborate
(edit) Having said that, you did say the 1704. I was addressing the problem of the other DAC which needs a positive current injected to center at the 2.00mA half-scale.
As far as current sources/sinks go, many will allow substantial filtering of the reference voltage that determines the current. Definitely a good thing to do, but at sufficiently low frequencies eventually the "1/f" component will render filtering otiose.
Oh I see for the TDA1541 which has the -2 mA offset.
Problem is that the Max6162 can only output around 0.5ma, so I think you would need a BJT between Outf and Outs, basically the same schematic as in the datasheet currentsource but Gs not connected to main ground, connected to the i/v input instead.
Looks a lot like the Preda simple Jfet CCS but with 127 minature transistors regulating the current and adding extra noise?
Also I believe the input impedance of your I/V stage would have to be below 75 ohms in order not to violate the 300 mv ground deviation rule from the datasheet.
Not sure why one would use this instead of the standard pedra jfet ccs for tda1541, educate me?
Looks a lot like the Preda simple Jfet CCS but with 127 minature transistors regulating the current and adding extra noise?
Also I believe the input impedance of your I/V stage would have to be below 75 ohms in order not to violate the 300 mv ground deviation rule from the datasheet.
Not sure why one would use this instead of the standard pedra jfet ccs for tda1541, educate me?
I know that I was just making the observation as to the limits. I believe that 300mV spec was misunderstood by the previous poster on the subject, it doesn't mean the Max can deliver the 2ma (on its own) offset needed for the tda1541, it relates to voltage, hence input impedance.
Shown on Ove's website, the rest of the website is worth checking out if you have a tda1541, lot of wisdom.
http://www.binatech.se/hem/Amps/TDA1541_tubed_CCDA.jpg
Unfortunately the original pedra website is no longer , but on the schematic above, see the simple jfet ccs right after the i-out, it is delivering the 2ma's that the TDA51541 needs. Now not regulated like the max 6126 implementation, but with 15R input impedance with the cen/zen we are going to be over and above the TDA1541 max compliance voltage regardless, so a drift af a few micro amps proabably isn't worth adding 127 transistors (max6126) if we are keeping with the simple low device count theme of the zen. Its a very good philosophy btw, so I guess that is why I am sort of jumping on this, plus the TDA1541 is near and dear to all of our hearts.
My datasheet says 10mA sink/source for the 6162, so no limitation there. EUVL I believe suggested somewhere in this thread that the 6162 was particularly low-drift, in response to someone complaining about warm-up times for their configuration.
As I say I would find other means, although I suspect using a voltage reference like the 6162 is not a bad piece for the puzzle.
When I needed a voltage reference for a complex system I used a JFET biased at its approximate zero-drain-current point, followed by a low-drift discrete buffer, and put the whole thing in a temperature-stabilized enclosure. It was better than needed by far, but I didn't want to take any chances. The closest thing to it "off-the-shelf" was the LM199 part, a temp-servoed buried zener arrangement, which was still much noisier. This was circa 1978, just to put it in context.
Very sorry for such an old Post revival, but could anyone explain what makes Stereo and 4 or 8 channels different from SEN / CEN point of view ? When you say double the number of JFet , you mean the CEN FETs or the CCS FETs?
Also, is it so critical that the VRef be exactly at Vcc/2 ?
In TwistedPear Legato IV, they just set the input offset by adjusting a trimmer until it is approximately at Vcc/2
..and the manual of the Legato says it's not that critical anyway (but maybe there are principle difference between it and the CEN/SEN that I don't catch)
Hi NIC,
I might be able to do it..... Only issue is I'm much better at designing PCBs than understanding how the Buffallo DAC works, .....
Actually I have already started to design the PCB for myself....I will try to make a drawing of what I have in mind and propose to the folks here for opinion / confirmation that I understood things correctly.
Then, if EUVL agrees that we use his design, we could make a mini Group Buy on that one...
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> could anyone explain what makes Stereo and 4 or 8 channels different from SEN / CEN point of view ?
The amount of current signal is being doubled when using 4 channels as compared to 8.
> When you say double the number of JFet , you mean the CEN FETs
Yes.
> Also, is it so critical that the VRef be exactly at Vcc/2 ?
It is critical in the sense that you need to adjust the Vref such that the output at the CEN/SEN is 0V.
> but maybe there are principle difference between it and the CEN/SEN that I don't catch
That is correct.
> I might be able to do it..... Only issue is I'm much better at designing PCBs than understanding how the Buffallo DAC works, .....
Please refer to the Group Buy thread.
http://www.diyaudio.com/forums/group-buys/196585-sen-cen-all-jfet-iv-converter-evaluation-pack.html
There are a couple of 9018 users (Vref version subscribers) who know what they are doing.
> Then, if EUVL agrees that we use his design, we could make a mini Group Buy on that one...
As said, there is already a version for 9018 users. See above.
Patrick
The amount of current signal is being doubled when using 4 channels as compared to 8.
> When you say double the number of JFet , you mean the CEN FETs
Yes.
> Also, is it so critical that the VRef be exactly at Vcc/2 ?
It is critical in the sense that you need to adjust the Vref such that the output at the CEN/SEN is 0V.
> but maybe there are principle difference between it and the CEN/SEN that I don't catch
That is correct.
> I might be able to do it..... Only issue is I'm much better at designing PCBs than understanding how the Buffallo DAC works, .....
Please refer to the Group Buy thread.
http://www.diyaudio.com/forums/group-buys/196585-sen-cen-all-jfet-iv-converter-evaluation-pack.html
There are a couple of 9018 users (Vref version subscribers) who know what they are doing.
> Then, if EUVL agrees that we use his design, we could make a mini Group Buy on that one...
As said, there is already a version for 9018 users. See above.
Patrick
Thanks ! and I suppose Stereo quadruples it
I had missed that one. My understanding is the GB is already closed... nevermind! I like to DIY boards, and you post http://www.diyaudio.com/forums/group-buys/196585-sen-cen-all-jfet-iv-converter-evaluation-pack-14.html#post2748881 to Nic questions answered the last question I had on floating supplies.
Thanks
Fred
yes the output impedance is different also when using 4 channels vs 8 as there are double the dacs in parallel. the dac is comprised of 8 dacs. in stereo mode the output Z is ~195R this means you will need to change the IV resistor if you want the same 3vrms output
also I suggest measuring your specific AVCC regulator, as its different depending on the time of production. anywhere from 3.3v to 3.6v+ so measure the AVCC pin on the shunt and divide by 2 for your gate bias
afaik all of the pins on the dac are 4v tolerant and the higher you go with AVCC the better the DNR (although i wouldn't recommend setting it to 4v, give some safe margin) so really as long as this matches the whole way through from the dac out through the IV stage you will be able to adjust for 0v
also I suggest measuring your specific AVCC regulator, as its different depending on the time of production. anywhere from 3.3v to 3.6v+ so measure the AVCC pin on the shunt and divide by 2 for your gate bias
afaik all of the pins on the dac are 4v tolerant and the higher you go with AVCC the better the DNR (although i wouldn't recommend setting it to 4v, give some safe margin) so really as long as this matches the whole way through from the dac out through the IV stage you will be able to adjust for 0v
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Thanks for the IV resistor tip (would never have thought of it)
I thought I got the VRef thing, but now I'm confused again
..... can't I just take Vcc from the DAC itself (or rather the shunt) and use a voltage divider to set VRef (and use that same VRef for every 4 channels) ?