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Old 16th April 2004, 06:54 PM   #71
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Quote:
Originally posted by till
And why not with an active element as a differential amp with gain < 1 so the signal would be present inverted and noninverted to feed 2 DACs for balanced operation?

I do not consider that as a good idea. Tomorrow I will receive the SN74HC86N exclusive or logic chips and I will play with the 2 TDA1541A you kindly send to me some time ago for a balanced operation . See the D1 schematich just before the PCM63 to know what I am thinkin. There , four EX OR ar used as buffer and as inverter for DATA in one chip.
The output stage will be D1 without buffer. I am expectin' good results.

Thanks
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Old 16th April 2004, 07:25 PM   #72
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that many parts like this TTL logic confuses me and is difficult for me to prototype. PCB.....
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Old 18th April 2004, 01:02 PM   #73
HtP is offline HtP  Netherlands
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I stated:

Current reference generator for the output current is between -5V and -15V. Output current from the dac comes out of pin 6, 25 via diode switches or comes out via the +5V pin 28 by darlingtons. This means that complementory output signals L+R flow in supply pin 28.

And Pedja responded:

I do not quite figure this. Three or 4 active divider pins are inside -15V- -5V range but the others are not.

Interesting note about pin 28.

Pedja

I made two statements.

1. Current reference generator for the output current is between -5V and -15V.

What was ment here is where the current 'reference' generator circuit is, that it is supplied between the -5V and the -15V pins. With other words, the supply voltage of the current reference is 10V. This current reference is the reference for all binary weigthed currents in the TDA1541(A). The supply rejection ratio for this current reference is not infinite, thus this 10V should be as constant as possible.

The binary weigthed currents in the TDA1541(A) are made accurate by the dem circuit, the voltages on the filters for this dem circuit are not direct related with the supply voltage of the current reference. The fact that (some of) these voltages are above the supply voltage of the current reference is not in conflict with my statement.

2. Output currents from the dac comes out of pin 6, 25 via diode switches or comes out via the +5V pin 28 by darlingtons. This means that complementory output signals L+R flow in supply pin 28.

The inner curcuit of the dac can be seen as a binairy controlled differential stage.
One output (the not used) flows in pin 28, thus +5V. The outher output in pin 6, 25. The sum of signal currents in pin 6, 25 and pin 28 is constant. That means that it is advantageous to bring the output currents in pin 6, 25 back into the +5V supply. That can be done by e.g copying the output current into the +5V supply. If done correct, the signal in the +5V decoupling capacitor completely disapears.

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Old 18th April 2004, 08:21 PM   #74
Pedja is offline Pedja  Serbia
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This leads mo to the conclusion a local decoupling between the pin 15 (-15V) and the pin 26 (-5V) could be welcome.

Also, putting aside the last possibility you mentioned, the pin 28 (+5V) should have nice AC path to the analog ground.

However, with existing decoupling of all the rails to ground and decoupling directly between +5V and -5V things are becoming a bit horrible.

Btw, it is not that I am asking for proofs but I am curious about the source of your info about 1541. Is it someone involved in the designing of this chip? Finally, I see you are in Eindhoven, maybe this means something?

To clarify/confirm the things spoken earlier, a low passing of the I2S lines is conventionally done using series resistors and capacitance of the inputs, but did I understand you, do you consider the shunting of HF current to the (digital) ground instead to the substrate as qualitatively significantly different thing?

Thanks,
Pedja
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Old 18th April 2004, 08:56 PM   #75
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Quote:
Originally posted by till
fine, i nearly understood this. Now could anybody please post the schematic of the circuit to get the TTL down to the desired voltages the TDA1541 likes best?
Oh yes, please
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Old 19th April 2004, 12:45 PM   #76
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Is this schematic ok ? Swings from 0,9V to 1,6V.
Attached Images
File Type: jpg level shifter.jpg (19.7 KB, 1879 views)
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Old 19th April 2004, 03:46 PM   #77
Bricolo is offline Bricolo  France
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and with R2=3K you'll get 1.3-1.5V

but maybe 3k is too much for the dataline
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Old 19th April 2004, 05:49 PM   #78
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Quote:
Originally posted by Pedja

Btw, it is not that I am asking for proofs but I am curious about the source of your info about 1541. Is it someone involved in the designing of this chip? Finally, I see you are in Eindhoven, maybe this means something?

Thanks,
Pedja
Yes, yes.

Quote:
Originally posted by Pedja

To clarify/confirm the things spoken earlier, a low passing of the I2S lines is conventionally done using series resistors and capacitance of the inputs, but did I understand you, do you consider the shunting of HF current to the (digital) ground instead to the substrate as qualitatively significantly different thing?

Thanks,
Pedja
Yes, it keeps the hf currents out of the chip.

regards,
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Old 19th April 2004, 06:02 PM   #79
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Quote:
Originally posted by Bernhard
Is this schematic ok ? Swings from 0,9V to 1,6V.
With R4 = 75 ohm, time constant is only 750psec. So R4 = 1k will give a time constant of 10nsec. For R1 I propose 4k7 with 5V logic input or 3k3 with 3V logic input. This will also reduce the load of the logic. It assures also that there is always current in the diodes.

I would prefer to use this circuit three times, for DATA, BCK and WS each. This avoids data dependence of slicing levels.

regards,
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Old 19th April 2004, 06:48 PM   #80
Bricolo is offline Bricolo  France
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Is there no problem in having sugh high impedances on the datalines?
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