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Valve DAC from Linear Audio volume 13
Valve DAC from Linear Audio volume 13
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Old 4th November 2017, 07:46 PM   #41
spaceistheplace is offline spaceistheplace
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Valve DAC from Linear Audio volume 13
I would be interested in a board. Could someone roughly estimate the total cost of the BOM? From a cursory look about $500 Euro?
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Old 4th November 2017, 11:22 PM   #42
MarcelvdG is offline MarcelvdG  Netherlands
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Rough estimate: 850 euros including supply transformers and FPGA board for the balanced version without the optional output signal transformers. That's assuming reasonably-priced valves, some brands are absurdly expensive.
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Old 5th November 2017, 04:36 PM   #43
leadbelly is offline leadbelly  Canada
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Valve DAC from Linear Audio volume 13
Quote:
Originally Posted by spaceistheplace View Post
I would be interested in a board.
Hi, if you are still interested, please sign up for the group buy here:
Interest for GB for MarcelvdG valve DAC
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Old 9th November 2017, 08:13 PM   #44
MarcelvdG is offline MarcelvdG  Netherlands
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Quote:
Originally Posted by randytsuch View Post
Slave mode would be fine, but would probably want "option 2", with support for different word to bit clock ratios.

At least this isn't the really complicated option lol
I've had a look at the Verilog code of the prefilter.v module that interfaces with the DIX4192 (see the attachments, I've renamed it to prefilter.txt because the forum doesn't allow .v). I wrote it more than a year ago, so it took me a while before I fully understood my own design again.

There are actually two things that need changing to support bit-clock-to-word-clock ratios different from 64. One is changing the code such that the incoming bits end up at the right place independent of the ratio of the bit clock to the word clock.

The other is generating the clocks that come out of prefilter.v (and go into the SRC4392) in a different way. Right now I derive them from the incoming bit clock, but I have to change that to the incoming word clock. This is a bit more complicated, especially since the frequency of the incoming word clock is too low for the Spartan 6 PLLs and the jitter can be too high for the Spartan 6 DCMs. I think I'll make a frequency-locked loop with a rate multiplier as numerically controlled oscillator.

Anyway, I'm looking into this, but it will take a while before I got it debugged and running.

Are there any specific signal sources and bit clock to word clock ratios you are interested in?
Attached Files
File Type: pdf prefilter_sketch.pdf (425.9 KB, 45 views)
File Type: txt prefilter.txt (8.9 KB, 15 views)
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Old 25th December 2017, 09:29 PM   #45
MarcelvdG is offline MarcelvdG  Netherlands
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Hi all,

Well, I just programmed my new configuration file into an FPGA board to see if it works. I haven't had a chance to test any of the new functions yet, but at least it is still functional: it is playing David Bowie's last CD right now.

If everything works as intended, these functions are added (with thanks to Randy for the discussion we had over PM about what functions would be useful):

I2S interface on the extension connector that can handle anything from 8 to 32 bits with a bit clock of 16 to 64 times the word clock, with de-emphasis and mute inputs and with support for DSD64 via DoP

Input that changes the I2S interface into a raw DSD interface

Support for DSD64 and DSD128 over the raw DSD interface

Merry Christmas everyone!

Last edited by MarcelvdG; 25th December 2017 at 09:32 PM.
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Old 26th December 2017, 03:59 PM   #46
MarcelvdG is offline MarcelvdG  Netherlands
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The I2S input works; attached to a Raspberry Pi model 3B running Volumio, I can use it as a generic I2S DAC. The de-emphasis also works, the raw DSD input still needs to be checked.
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Old 26th December 2017, 04:21 PM   #47
leadbelly is offline leadbelly  Canada
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Very very cool!
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Old 29th December 2017, 09:11 AM   #48
MarcelvdG is offline MarcelvdG  Netherlands
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The raw DSD64 and DSD128 interface also works now. I connected a simple analogue sigma-delta modulator to it and played some dance-hall reggae through the chain.

The day before yesterday it didn't work at all due to a silly bug; I had specified three-bit patterns as 010 and 011 instead of 3'b010 and 3'b011, which means they were interpreted as decimal 10 and 11. As a three-bit pattern can never be ten or eleven, the Xilinx programs recognized it as redundant logic and optimized out a part of the design (-;
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Old 3rd January 2018, 02:08 PM   #49
MarcelvdG is offline MarcelvdG  Netherlands
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The latest Verilog code and MCS file can now be downloaded from the Linear Audio website:

Downloads | Linear Audio
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Old 16th January 2018, 08:31 PM   #50
MarcelvdG is offline MarcelvdG  Netherlands
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There was an annoying bug in the Verilog code of version 2 that made DSD playback unreliable. I fixed it and Jan Didden put the updated code on his website: Downloads | Linear Audio or https://linearaudio.net/sites/linear...version2p1.zip
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