I think this MCU+display could be made more universal and allow control over DAC also (for those using FIFO with a DAC with SPI/I2C interface). I have emailed you ...
Chris
Hi Ian,
i would like to run it direct with my Salas SSLV. If it´s only the one onboard LDO and no other parts, than i could handle it.
But i saw that more guys are interested in the direct 3.3V mod., so a photo will be helpful.
My I2S backdoor on the S/PDIF runs perfect. It´s only the source selecting i was talking about
Cheers,
Oliver
Passive/Active Hybrid Battery Monitor Suggestions
I have been thinking of ways to get the battery monitor to monitor and shut down to prevent over discharge conditions damaging batteries, without defeating isolation during listening times.
I am not sure if this should be part of a 'FIFO controller' uController design mentioned above, or a revision to the battery monitor board, or a mix of the two.
The FIFO J13 connector provides a signal that indicates period of silence. I am not sure of the latency of this signal, how quickly is this status changed Ian?
During period of silence, could a relay be toggled such that an active battery monitor chip (or a simple comparator) is able to check the battery? Perhaps an optically isolated solid state relay since this relay will see far more operations than any of the other relays in this system.
I have in mind that it could work as follows:
- silent status received, toggle relay to switch in the battery monitor circuit
- silent status goes to a 555 timer delay to ensure that the battery monitor has time to properly evaluate the battery low status, eliminate transient conditions
- then an AND or NAND on the delayed silent signal and the comparator/battery monitor chip's output should provide a signal that can be used to disconnect the battery
I haven't thought through a proper lockout timer process yet. May need to provide an output of the 'battery low shutdown' condition for use by other connected equipment (other battery monitor boards, input to MCU for status reporting of each battery supply etc).
The above adds the following components to the current design:
- active monitor/comparator
- current 555 timer for inrush current can become a dual 555 timer SOIC16 instead of SOIC8
- single and gate chip - could be SOT package
- passive components for setting trigger levels and delay timer.
This shouldn't result in unmanageable levels of additional complexity compared to the existing schematic and can be an additional 'optional' portion on a revised PCB.
I know some of this was discussed in non-specific posts a while back, I've tried to come up with a cohesive solution that tackles it in a relatively simple way without making it unnecessarily complex.
Cheers,
Chris
I have been thinking of ways to get the battery monitor to monitor and shut down to prevent over discharge conditions damaging batteries, without defeating isolation during listening times.
I am not sure if this should be part of a 'FIFO controller' uController design mentioned above, or a revision to the battery monitor board, or a mix of the two.
The FIFO J13 connector provides a signal that indicates period of silence. I am not sure of the latency of this signal, how quickly is this status changed Ian?
During period of silence, could a relay be toggled such that an active battery monitor chip (or a simple comparator) is able to check the battery? Perhaps an optically isolated solid state relay since this relay will see far more operations than any of the other relays in this system.
I have in mind that it could work as follows:
- silent status received, toggle relay to switch in the battery monitor circuit
- silent status goes to a 555 timer delay to ensure that the battery monitor has time to properly evaluate the battery low status, eliminate transient conditions
- then an AND or NAND on the delayed silent signal and the comparator/battery monitor chip's output should provide a signal that can be used to disconnect the battery
I haven't thought through a proper lockout timer process yet. May need to provide an output of the 'battery low shutdown' condition for use by other connected equipment (other battery monitor boards, input to MCU for status reporting of each battery supply etc).
The above adds the following components to the current design:
- active monitor/comparator
- current 555 timer for inrush current can become a dual 555 timer SOIC16 instead of SOIC8
- single and gate chip - could be SOT package
- passive components for setting trigger levels and delay timer.
This shouldn't result in unmanageable levels of additional complexity compared to the existing schematic and can be an additional 'optional' portion on a revised PCB.
I know some of this was discussed in non-specific posts a while back, I've tried to come up with a cohesive solution that tackles it in a relatively simple way without making it unnecessarily complex.
Cheers,
Chris
Hi, Chris
The silence signal will only happen when Fs is switching or FIFO is lost lock. So, it usually takes long time.
I suggest use a passive voltage meter monitoring the battery. Any active component will generate noise. But we have to figure out how to protect battery from over discharge beside shut down the power manually when battery is low.
I'll use a bigger battery pack together with passive monitoring gauge and make sure battery being charged all the time while system is off.
Let me know for any good idea.
Regards,
Ian
Ahhh okay, I was hoping it was an indication of extended period of silence in the i2s stream, which I was hoping might happen often enough for our purpose. I was wrong though. Fs switch and unlock don't happen anywhere near often enough for our needs as you say.
Back to the drawing board for new/more ideas.
Chris
Actually my FPGA logic has that I2S zero detecting signal inside which might be the one you want, I just didn't assign a pin for it
.Ian
Actually my FPGA logic has that I2S zero detecting signal inside which might be the one you want, I just didn't assign a pin for it
Ian
That sounds like exactly what I want
Hi Ian,
I upgraded to double dual clock with crystek 45Mhz & 49Mhz. The sound improved, but I get the error when playing the files with sample rate 44.1 Khz & 96 Khz .
- Sample Rate 96KHz :
All times playing 96kHz files then all Leds on Clock board is flashing. On FIFO, the Led "Emty" is light. No sound.
- Sample Rate 44.1kHz :
On Clock board, The Leds 48Khz & 96Khz is light. On FIFO, the Led "Emty" is light. No sound.
But I noticed that when I playing the file 88khz or 176 Khz, then continue to playing the files 44.1 Khz is ok.
I read but not seen anyone with this error.
Ah, it is necessary to add the 100n capacitor and 1uF for Crystek adapter board ?.
I use PC with Jriver 18 + Amanero .
Thank you .
I upgraded to double dual clock with crystek 45Mhz & 49Mhz. The sound improved, but I get the error when playing the files with sample rate 44.1 Khz & 96 Khz .
- Sample Rate 96KHz :
All times playing 96kHz files then all Leds on Clock board is flashing. On FIFO, the Led "Emty" is light. No sound.
- Sample Rate 44.1kHz :
On Clock board, The Leds 48Khz & 96Khz is light. On FIFO, the Led "Emty" is light. No sound.
But I noticed that when I playing the file 88khz or 176 Khz, then continue to playing the files 44.1 Khz is ok.
I read but not seen anyone with this error.
Ah, it is necessary to add the 100n capacitor and 1uF for Crystek adapter board ?.
I use PC with Jriver 18 + Amanero .
Thank you .
Attachments
This error is caused by U1 jumper on Clock board , (long time I think caused by software & firmware
Looks good. Glad you fix it. Both hardware and software were confirmed many time should be no problem
.Nice weekend.
Ian
Greetings,
I reolved my issue with the Si clock and synching the es9023 dac. I noticed that the clcok was set to 90/98 Mhz. The es9023 didn't like that speed. I switched to 45/49 and all is good. tried 44.1 and 48khz files without any glitch.
Now, I would like to drive a dual mono with the Si clock board in asynch mode for now. So I soldered the ufl on the second I2S outputs. I get no signal on the second set. Only one channel (N the top set) is functionning.
Is there anything else needed other than the ufl connectors? Jumper I am missing perhaps?
regards.
I reolved my issue with the Si clock and synching the es9023 dac. I noticed that the clcok was set to 90/98 Mhz. The es9023 didn't like that speed. I switched to 45/49 and all is good. tried 44.1 and 48khz files without any glitch.
Now, I would like to drive a dual mono with the Si clock board in asynch mode for now. So I soldered the ufl on the second I2S outputs. I get no signal on the second set. Only one channel (N the top set) is functionning.
Is there anything else needed other than the ufl connectors? Jumper I am missing perhaps?
regards.
Hi necplusultra,
Here is the schematic of the output section of the Si570 clock board. It would easy for you to address the problem with it.
Hope it helps.
Regards,
Ian
Attachments
I just noticed this hadn't been addressed. You should not need those caps when using the Crystek XO. The Crystek units have decoupling internally I believe so do not require additional decoupling on the adapter PCB.
Thanks you ,
I thought why not practical test?
. After listening to both cases, I likes the sound with no capacitors . The sound more open, especially in high frequencies .