TDA1541 DEM reclocking

[tubee]

Check ecdesigns non os 1541 dac project for a clue

Nice to hear you have an improvement hollowman

[hollowman]

Originally posted by hollowman
I just installed Tubee's version of DEM into a CD-60. Definite improvement....

Just wanted to clarify that the Tubee DEM I implemented does not involve re-clocking WS or BCK as per Henk's original DEM ckt. On this issue (i.e., DEM of pin 16/17 only), I'm confused about the efficacy of Henk's WS+DEM design: why not DEM in and of itself?

As a followup, I replaced Tubee DEM with Henk DEM (w/o WS or BCK reclocking, of course); the former was clearly better, Henk's was simply "different" from the orig cap.

My main point is that while I feel Henk was truly onto something with DEM of pin 16/17, WS and/or BCK reclocking should, by themselves (and specifically with 7220), yield improvement.

Comments are appreciated!

[-ecdesigns-]

I'm confused about the efficacy of Henk's WS+DEM design: why not DEM in and of itself?

The integrated DEM clock oscillator is a free running oscillator with a frequency between 100 and 300 KHz. This creates a second clock source (together with the bit clock) so inter-modulation occurs. This inter-modulation varies as the DEM oscillator drifts / jitters.

When the TDA1541A receives data, the DEM oscillator frequency will vary with the data pattern (very high jitter), due to on-chip crosstalk.

The DEM clock drives an on-chip shift register that controls the active current dividers that are part of the Dynamic Element Matching circuit. If the DEM clock frequency varies dynamically, bit errors will increase due to incorrect time averaging.

DEM clock issues are best tested with -40 ... -70dB recordings (Sheffield A2TB test disk).

I attached some oscillograms that illustrate this problem. Upper picture shows how the DEM oscillator jitter (frequency modulation) when using the data sheet application. The picture on the bottom shows an externally triggered DEM clock.


One solution for this problem is preventing the DEM oscillator from oscillating:

pin 16 > 2K2 resistor > -15V
pin 17 > 2K2 resistor > -15V

Then injecting a DEM clock that runs fully synchronous with the bit clock (176.4 KHz, 352.8 KHz, 705.6 KHz, 1.4112 MHz or 2.8224 MHz.).

This is done by creating both a non-inverted and an inverted low jitter clock 352.8 KHz for example). Then injecting these two signals as follows:

non-inverting clock > 10K Ohm > pin 16
inverting clock > 10K Ohm > pin 17

DEM clock frequency also depends on active divider decoupling cap properties and placement. It's best to use smallest possible (SMD) film caps, and use shortest possible connections (every mm counts here). It's also possible to solder the active divider decoupling caps directly to the TDA1541A pins, and route the capacitor GND connections straight to pin 5 (analogue ground).

External DEM clock frequencies of up to 2.8224 MHz are possible when active divider decoupling is done correctly.

Now the DEM oscillator circuit is forced to run in sync with the external DEM clock, this eliminates inter-modulation, greatly reduces DEM clock jitter, and improves time averaging, resulting in lower bit errors.


The I2S signals are THE major source for on-chip interference (noise / inter-modulation with the audio signal).

Therefore it's absolutely necessary to attenuate the RF power levels of these signals to lowest possible values while maintaining reliable DAC chip operation.

The signal amplitude can be reduced from 5Vpp to only 400mVpp, but approx. 1.2V DC bias voltage is required. So the 400mVpp has to be super-imposed on this DC bias voltage. The signal of WS and DATA can also be band-limited for minimizing RF energy:

WS and DATA inputs are connected as follows:

input > 3K3 > +5V.
input > 1K > GND.
input > 3K3 > output from I2S source.


For the bit clock (BCK) we can't band limit as this might increase jitter, so different values are used here:

input > 330 > +5V.
input > 100R > GND.
input > 330 > output from I2S source.

It's also possible to use a dynamic jitter attenuator for BCK, this circuit attenuates BCK, and dynamically manipulates the exact moment the TDA1541A triggers. This way, sample jitter amplitude can be slightly reduced.

[samoloko]

I want to make 1541a NOS with reclock
I will build this design http://pc.watch.impress.co.jp/docs/2...1a_1fs_v11.jpg and will parallel another TDA1541a

there Is something I am not sure regarding reclocking
why schematic Is so simple done - only TCXO and 74HC0404 compared to the schematics on this thread - Henk, Ecdesigns, Toobee
would anybody explain

[-ecdesigns-]

why schematic Is so simple done - only TCXO and 74HC0404 compared to the schematics on this thread - Henk, Ecdesigns, Toobee
would anybody explain

The schematic shows CS8412 running in slave mode. When both source clock and clock module feeding CS8412 and TDA1541A aren't running exactly in sync, samples will be dropped or repeated.

Since both clocks run in different time domains, clocks aren't synchronized as required.

This will lead to repeated or dropped samples, resulting in audible clicks during playback. These are clearly audible when using a sine wave test signal.

Apart from sample timing jitter issues, the schematic has many flaws that will prevent optimal performance

[bbp]

so loooong a thread, but how about the TR with 74HC74?
I think the faster 74F74 should work better

[samoloko]

Hi John

would you please tell me how I can Improve that flaws

[Sandor]

Hello ecdesigns,
could you please post the latest (and supposedly best) DEM reclock circuit? In another thread I have read that you have obtained the best results using a clock derived from WS.
Regards.

Paul

[-ecdesigns-]

would you please tell me how I can Improve that flaws

1) Don't use SPDIF when possible, it degrades sound quality. Try to use direct I2S whenever possible.

2) Use discrete voltage regulators for +5V, -5V, and -15V, LM78xx, LM79xx, LM317, LM337, and TL431-based regulators aren't suitable for this application and cause significant sound quality degradation. I could post some schematics of suitable regulators.

It's best to create high impedance in series with the power supply in order to block mains interference. Minimum requirement is a 9th order LC filter.

3) Slave the transport and put the master clock in the DAC. Use a synchronous reclocker (pico gate SMD part) for synchronously reclocking BCK with the master clock. This isn't always possible (depends on source properties). Best solution could be a concept similar to the SD-player project.

4) Use extreme low jitter master clock with highest possible PSRR and highest possible load immunity. Off the shelf clocks aren't suitable for these demanding applications. The master clock must be fed from a heavily filtered power supply (at least 9th order LC filter). The chokes used for power supply filtering must have lowest possible self capacitance, this means constructing special hybrid chokes.

5) Use I2S attenuators, this greatly reduces ground-bounce at the TDA1541A I2S input circuits. Use dynamic jitter attenuator circuit for BCK. I could post latest version of these circuits.

6) Don't ever use Op-amps in the signal path, these greatly reduce dynamic resolution. Placing two of these dynamic resolution killers in series is pretty fatal for audiophile sound quality. Major reasons for this are many on-chip components in the signal path, global feedback, high open-loop gain, and the use of both current sources and current mirrors. Best solution (for obtaining highest possible dynamic resolution) is using pure passive I/V converter without any semiconductors nor tubes. TDA1541A is capable of producing up to 550mVpp low distortion signal across a 140 Ohm passive I/V resistor, provided a 2.5mA bias current is used. This bias current can be injected using a resistor, or a resistor in series with a suitable hybrid choke. If amplification is required, tubes are the next best solution, followed by FETs.

The passive I/V resistor must provide extreme low noise levels (high-wattage wire-wound type), must be non-inductive and must have lowest possible self capacitance. I now use home made non-inductive wire-wound resistors that are wound using honeycomb winding method for providing extreme low self capacitance and lowest possible Eddy current losses.

7) When using NOS, don't use any form of filtering as this introduces uncorrectable phase shifts. This however requires large bandwidth processing (>80 KHz) up to the speakers. If a NOS DAC produces edge on vocals, this is likely to be caused by timing jitter and poor dynamic resolution of connected audio equipment, speakers included.

8) Use a suitable low jitter external DEM clock instead of the on-chip DEM oscillator that produces very high jitter. The DEM clock signal inter-modulates with BCK, this causes sample timing jitter increase. The latest circuit I have used is a simple diode-resistor injector that is fed with 44.1 KHz WS signal.

9) Pay extra attention to GND routes, use very low impedance wiring (litz wire) and a star ground.

10) Use smallest possible 100nF bypass film caps (SMD) and place these underneath the TDA1541A chip for shortest possible connections, every millimeter counts!

11) Never share decoupling cap (14 x 100nF) ground routes with other signals.

[samoloko]

thx John for that tips

since I try to learn about reclocking I would be thankful to point me to some reclocking schematic - some simple and effective

as I see there Is two reclock types used - 1 reclocking I2S - BCK, WS, data;
2 DEM reclocking TDA1541 pin 16 and 17

In order of priority what signals are best to reclock - can all this be done with one XO supplied with good voltage regulator and given 2 or 3 pcs logic chips

can you confirm that this circuit TDA1541 DEM reclocking will work