Hi,
This thread is intended to be a take off of the "Development of a "reference" class D starting point" thread, for which all the background information of this project can be found at:
http://www.diyaudio.com/forums/showthread.php?s=&threadid=36852
It is as complete as I care to make it, though I've included no by-passing on the driver power supplies, along with a few other minor changes which would be required for a real implementation of it.
In this first post I will include extensive simulation results, to be followed with a FFT done with 100mV input at 1Khz, then I'll provide the circuit schematic, both in the form of a bitmap or jpg, and the pspice *.DSN file.
I do not intend to produce a pcb design for this, so if anyone decides to make one, and gets it working well, please contribute.
All the simulations for which the results you are about to see, have been done with default pspice options, and being spice, obviously, need to be taken with a grain of salt, or two.
However, I'm very pleased with the results it shows. That's not to say it can't be improved on, and anyone who cares to is invited to contribute there as well.
Regards,
Chris
This thread is intended to be a take off of the "Development of a "reference" class D starting point" thread, for which all the background information of this project can be found at:
http://www.diyaudio.com/forums/showthread.php?s=&threadid=36852
It is as complete as I care to make it, though I've included no by-passing on the driver power supplies, along with a few other minor changes which would be required for a real implementation of it.
In this first post I will include extensive simulation results, to be followed with a FFT done with 100mV input at 1Khz, then I'll provide the circuit schematic, both in the form of a bitmap or jpg, and the pspice *.DSN file.
I do not intend to produce a pcb design for this, so if anyone decides to make one, and gets it working well, please contribute.
All the simulations for which the results you are about to see, have been done with default pspice options, and being spice, obviously, need to be taken with a grain of salt, or two.
However, I'm very pleased with the results it shows. That's not to say it can't be improved on, and anyone who cares to is invited to contribute there as well.
Regards,
Chris
Schematic in .bmp format.
A few notes here..
Note the 5K resistors used to bias the op amps. It was more of a proof of concept thing than anything else, it shows a worthy improvement in simulation, so I left them in. This schematic is exactly what produced the test results given in post #1.
The OPA627 ties to the positive rail, as the datasheet has a diagram of its internals I think it was the proper choice, simulation backs that up. As the OPA134 did not have such a schematic of its internals in the datasheet, it was biased to the negative rail through an educated guess, and what simulated best.
Being spice, since they're both tied to a perfect voltage source, it simulates a perfect current source. For a real implementation I'd change that to a cascode Jfet + bias resistor, which I think is the most robust way of doing it. There's alot of info out there on how to do it.
Also the IRF540 mosfets won't do. I'd recommend trying something like Fairchild's FDB3632 for it, as a starting point. It's a 100V 80A device with 0.009 Ohms Ron with Qg total of 84nC, should have a good charge ratio as well but I didn't check. They do provide a model of it, but from what I've experienced, they've tried to make the models so advanced that I've found it impossible to force them to converge.
A few notes here..
Note the 5K resistors used to bias the op amps. It was more of a proof of concept thing than anything else, it shows a worthy improvement in simulation, so I left them in. This schematic is exactly what produced the test results given in post #1.
The OPA627 ties to the positive rail, as the datasheet has a diagram of its internals I think it was the proper choice, simulation backs that up. As the OPA134 did not have such a schematic of its internals in the datasheet, it was biased to the negative rail through an educated guess, and what simulated best.
Being spice, since they're both tied to a perfect voltage source, it simulates a perfect current source. For a real implementation I'd change that to a cascode Jfet + bias resistor, which I think is the most robust way of doing it. There's alot of info out there on how to do it.
Also the IRF540 mosfets won't do. I'd recommend trying something like Fairchild's FDB3632 for it, as a starting point. It's a 100V 80A device with 0.009 Ohms Ron with Qg total of 84nC, should have a good charge ratio as well but I didn't check. They do provide a model of it, but from what I've experienced, they've tried to make the models so advanced that I've found it impossible to force them to converge.
Hi,
If I saved it as a gif there'd be a loss of quality and the ability to zoom right in would be lost, which means no values would be seen.
Wasn't happy with the biasing schemes I had tried for the cascode, they weren't very elegant, and that seemed to work great, I hadn't realized it would cause the other transistor to saturate. Might look into a clamp circuit . Hmmm... two diodes might do it... but I need sleep. I'll give it more thought later.
Thanks for pointing that out,
Regards,
Chris
If I saved it as a gif there'd be a loss of quality and the ability to zoom right in would be lost, which means no values would be seen.
Wasn't happy with the biasing schemes I had tried for the cascode, they weren't very elegant, and that seemed to work great, I hadn't realized it would cause the other transistor to saturate. Might look into a clamp circuit . Hmmm... two diodes might do it... but I need sleep. I'll give it more thought later.
Thanks for pointing that out,
Regards,
Chris
Bruno Putzeys said:
I wasn't talking about jpg either.... it is 5AM though.
You're right of course, no quality is lost. I'm also wrong in that you can't zoom in with them, you can.
A problem with Gifs (and jpeg) I've encountered in the past is, while compressed very well, they sometimes wind up being too big, and further zipping them does nothing, or makes them bigger, so I just tried zipping the bmp first and it was a decent size.. out it went.
Anyway, back to business, I tried the two diode idea, elegant as I can think of..
DC COMPONENT = 7.427910E-04
TOTAL HARMONIC DISTORTION = 5.485285E-03 PERCENT
That's 500mV input at 20Khz, looks great but shoot through is through the roof now, those results are not comparable.
It needs to be re optimised, but not today.. kind of pointless doing it anyway since spice isn't very exact, I kind of view it as a good ballpark figure to start with in a real circuit, meaningless as it is.
Ah well, here's the change I made, should do the trick.
Regards,
Chris
PS:
The image that you have attached is too big. Please make it no bigger than 800 x 1200.
Siiiiiiiiiiiigh
Better, but there is notthing that supresses common mode. It may not do any harm, but the opamps driving the diff stage may go into klipping. Then its a problem.
It may bee a god idea to start with a singel amp before you go for a balanced amp.
And the diff is near to transistors, not to exspensive to fix that 'problem'.
In spice all the components are equal, this is not so in real life as you say.
It may bee a god idea to start with a singel amp before you go for a balanced amp.
And the diff is near to transistors, not to exspensive to fix that 'problem'.
In spice all the components are equal, this is not so in real life as you say.
Konrad said:
Hi,
Nothing that suppresses common mode? Please elaborate, sounds interesting. There should be no common mode on the feedback signals. Other than that they're far from clipping. 1V differential input max, easily adjusted via the gain resistor in the input stage.
Parts were selected with +- 30 volt rails in mind, not 35 or 40. Parts selected are all that limits it from higher power.
Half bridge versions are in the other thread.
If you have any concrete improvements in mind please post them.
Regards,
Chris
This seems to work!
Basic circuit without classd4sure's input stage.
The input/controll-cuircuit shown by classd4sure would improove performance as open loop gain also in higher.
Abt the open loop gain have someone tried higher open loop gain?
I mean like replacing the resistors R121 and R122 with smal caps in Classd4sure's input stage ?
Basic circuit without classd4sure's input stage.
The input/controll-cuircuit shown by classd4sure would improove performance as open loop gain also in higher.
Abt the open loop gain have someone tried higher open loop gain?
I mean like replacing the resistors R121 and R122 with smal caps in Classd4sure's input stage ?
Attachments
Hi Chris & Konrad,
Nicely done to both of you - a good starting point - and clever CM balance Konrad
Output stage needs a bit more work - to make it faster & hence reduce the switching losses (how about adding a EF buffer with say FMMT617 / 717) - you could also add feedforward from the buffered driver to reduce the effects of circuit capacitances in the level shifter section.
John
Nicely done to both of you - a good starting point - and clever CM balance Konrad
Output stage needs a bit more work - to make it faster & hence reduce the switching losses (how about adding a EF buffer with say FMMT617 / 717) - you could also add feedforward from the buffered driver to reduce the effects of circuit capacitances in the level shifter section.
John
Hi,
In fact giving just a tiny bit more thought, you would only want to speed up Toff (PNP) so something with good Gain at high current like a FMMT717 / 718.
Ton (NPN) could be handled by a “limited” Current / Gain device – like BC something….
This would result in slower Ton times (nice "Soft" deadtime), and faster Toff times to compensate for Toff Delay.
With the extra EF stage you might also want to AC couple the output devices to swing the Gate to zero – or there about, this would reduce Enhancement voltage, but I would recommend 10V at Max – I normally only Enhance my output devices to about 9V – it’s a balance between RdsOn losses, and increased switching losses due to Toff Delay.
John
In fact giving just a tiny bit more thought, you would only want to speed up Toff (PNP) so something with good Gain at high current like a FMMT717 / 718.
Ton (NPN) could be handled by a “limited” Current / Gain device – like BC something….
This would result in slower Ton times (nice "Soft" deadtime), and faster Toff times to compensate for Toff Delay.
With the extra EF stage you might also want to AC couple the output devices to swing the Gate to zero – or there about, this would reduce Enhancement voltage, but I would recommend 10V at Max – I normally only Enhance my output devices to about 9V – it’s a balance between RdsOn losses, and increased switching losses due to Toff Delay.
John
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