Thanks
I've not looked for a while, been doing "normal" amps, and it came as a bit of a shock, to say the least.
I'll go back over the other thread to parts I've missed...
A simple stripped down version would be good to try, I have a simulator, so I could do some experimenting. I think it would be useful to others like myself who were following that thread.
Cheers
I've not looked for a while, been doing "normal" amps, and it came as a bit of a shock, to say the least.
I'll go back over the other thread to parts I've missed...
A simple stripped down version would be good to try, I have a simulator, so I could do some experimenting. I think it would be useful to others like myself who were following that thread.
Cheers
Okay,
I'll post it to the other thread later today. It's missing a few changes I made so I need to update it, I'll leave it to you to add the power regulator I used as it doesn't simulate with it, likely because it's biased to the negative rail. There are better versions to be found on that thread by far, but it's with parts I had around so that's what I used.
Here's some sim results of my next circuit, which I'll soon be posting here. It's not at all very different from the previous one and I think it's where I'll leave it, final version.
Gain 55, input 0.3v 20Khz and 0.6v 7.2KHz series connection, exactly like Konrad's, only showing more signals. Namely, power switching signals, all the mosfet current signals going to the output inductors, scaled input for your viewing pleasure and riding next to the output. Sure looks like a solide performer.
Cheers,
Chris
I'll post it to the other thread later today. It's missing a few changes I made so I need to update it, I'll leave it to you to add the power regulator I used as it doesn't simulate with it, likely because it's biased to the negative rail. There are better versions to be found on that thread by far, but it's with parts I had around so that's what I used.
Here's some sim results of my next circuit, which I'll soon be posting here. It's not at all very different from the previous one and I think it's where I'll leave it, final version.
Gain 55, input 0.3v 20Khz and 0.6v 7.2KHz series connection, exactly like Konrad's, only showing more signals. Namely, power switching signals, all the mosfet current signals going to the output inductors, scaled input for your viewing pleasure and riding next to the output. Sure looks like a solide performer.
Cheers,
Chris
I got a chance to look at the schematic diagrams. Konrad, your discrete comparator/cascode certainly has evolved beyond what I can follow without extended examination. 
Chris, am I missing something about the base connections of your cascode transistors? Unless I am experiencing a mental block, I would say that no current can flow out of their collectors.
Chris, am I missing something about the base connections of your cascode transistors? Unless I am experiencing a mental block, I would say that no current can flow out of their collectors.
subwo1 said:I got a chance to look at the schematic diagrams. Konrad, your discrete comparator/cascode certainly has evolved beyond what I can follow without extended examination.
Chris, am I missing something about the base connections of your cascode transistors? Unless I am experiencing a mental block, I would say that no current can flow out of their collectors.
Hi subw01, are you referring to the first schematic or the second revised one after I added the extra bias diodes?
Hello again
(somtimes i belive my nick should have been 'common mode')
The circuit seems too make common mode distortion dependent of peak and slewing, it shore looks like 3'rd harmonics when watcing cmmr signal. I find it not too bee, but rather dependent of switching "intensity/density" . Anyone exsperience the same?
When simulating on a Modified 'one' with modified CMMR-stage it seem to bee possible to reject this 'phenomen'.
At the same time the idea of bleeding psu for the high side driver from high side psu, using common mode rejektion stage to compensate for it, the common mode is increasing a tiny litle bit. Still lower (significantly lower) than without my modified CMMR stage.
BTW
my previusly posted delayed timer must bee considered as a principal drawing for redusing shot thru in the output dev. In outputs Ton is naturaly shorter than Toff, and neads too bee compensated for.
(somtimes i belive my nick should have been 'common mode')
The circuit seems too make common mode distortion dependent of peak and slewing, it shore looks like 3'rd harmonics when watcing cmmr signal. I find it not too bee, but rather dependent of switching "intensity/density" . Anyone exsperience the same?
When simulating on a Modified 'one' with modified CMMR-stage it seem to bee possible to reject this 'phenomen'.
At the same time the idea of bleeding psu for the high side driver from high side psu, using common mode rejektion stage to compensate for it, the common mode is increasing a tiny litle bit. Still lower (significantly lower) than without my modified CMMR stage.
BTW
my previusly posted delayed timer must bee considered as a principal drawing for redusing shot thru in the output dev. In outputs Ton is naturaly shorter than Toff, and neads too bee compensated for.
Konrad said:
I am not sure if your problem is related to simulations I did a while back in which the filters were not being damped in common mode by the feedback loops. At least most of the problem cancels across the speaker, but I still suspect a substantial increase in distortion occurrs. You can lower the amplitude with zeobel networks at each output.
I wonder if it is possible to modify the feedback loops so that they can "see" and compensate for the problem. I guess the common mode rejection stage you mentioned has that purpose. Since I think your circuitry has advanced beyond where my simulated ones were, my thoughts may not be too useful for your situation..
classd4sure said:
We are all waiting
On shot thru:
like some said somwere around here:
Not letting the outputs reverse conduct (like the internal diode is conducting) makes it slower turning too stop as the next halve is abt to conduct.
paralelling internal reverse diode with fast switching lov Vff giver remarkable simulation improovements.
as for clarity: I analysed one side of the H- bridge
Here is for the upper plot:
(IS(M4)+IB(M4))-5 = sorse current from upper output
(IS(M5)+IB(M5))-5 = sorse current lover halve output
I(D271)-5 = paralell diode current......
(Offset by +/- 5A for furter clarity)
Lower plot:
Pulse with modulation shown
Note R19:1 is the voltage taken midway of the load ( 4Ohm ) ie the common mode output.
innput ( V(V5:+,V4:-] ) and output [ V(R62:2,R18:1)/23.64] are scaled to the same size for comparison.
Hi,
Just a quick update since I promised a new revision awhile back. My extensive simulating proved it to be garbage(it failed in power dissipation). I've finally got it fixed, you'll all get to see it soon. Seems promissing thus far, I'm going to tweak it up a bit.
Might add the floating supplies as well, see how it goes.
Cheers
Just a quick update since I promised a new revision awhile back. My extensive simulating proved it to be garbage(it failed in power dissipation). I've finally got it fixed, you'll all get to see it soon. Seems promissing thus far, I'm going to tweak it up a bit.
Might add the floating supplies as well, see how it goes.
Cheers
Hi,
Just a quick update.
Optimising is comming along well.
Fs is now ~550Khz max due to proper impedance matching of my differential amps. I was shocked no one had mentioned that
Anyway it is a bit higher but I don't think unacceptably high.
I think you guys will appreciate the modifications I've made to the comparator.
Cut off is about 40Khz, it'll do a full power square wave at 20Khz nicely.
Here's some sim results you can look at
FS~550Khz Max
Fc Effective~ 40Khz
________________________________________________
100mV @ 1Khz, 8W pk
TOTAL POWER DISSIPATION 2.51E+00 WATTS
DC COMPONENT = -7.956208E-05
TOTAL HARMONIC DISTORTION = 1.430064E-02 PERCENT
_________________________________________________
200mV @ 1Khz, 32W pk
TOTAL POWER DISSIPATION 2.51E+00 WATTS
DC COMPONENT = -3.271441E-05
TOTAL HARMONIC DISTORTION = 6.161156E-03 PERCENT
__________________________________________________
300mV @ 1Khz, 70W pk
TOTAL POWER DISSIPATION 2.51E+00 WATTS
DC COMPONENT = -3.927749E-06
TOTAL HARMONIC DISTORTION = 1.053756E-02 PERCENT
__________________________________________________
400mV @ 1Khz, 124W pk
TOTAL POWER DISSIPATION 2.51E+00 WATTS
DC COMPONENT = -1.381230E-04
TOTAL HARMONIC DISTORTION = 1.244735E-02 PERCENT
__________________________________________________
500mV @ 1Khz, 193W pk
TOTAL POWER DISSIPATION 2.51E+00 WATTS
DC COMPONENT = -2.008052E-05
TOTAL HARMONIC DISTORTION = 1.324213E-02 PERCENT
__________________________________________________
So yeah, depending on the speed of my PC and if I get any more ideas to try out, I might post the circuit tomorrow.
So who's going to make the PCB art??
Cheers
Chris
Just a quick update.
Optimising is comming along well.
Fs is now ~550Khz max due to proper impedance matching of my differential amps. I was shocked no one had mentioned that
Anyway it is a bit higher but I don't think unacceptably high.
I think you guys will appreciate the modifications I've made to the comparator.
Cut off is about 40Khz, it'll do a full power square wave at 20Khz nicely.
Here's some sim results you can look at
FS~550Khz Max
Fc Effective~ 40Khz
________________________________________________
100mV @ 1Khz, 8W pk
TOTAL POWER DISSIPATION 2.51E+00 WATTS
DC COMPONENT = -7.956208E-05
TOTAL HARMONIC DISTORTION = 1.430064E-02 PERCENT
_________________________________________________
200mV @ 1Khz, 32W pk
TOTAL POWER DISSIPATION 2.51E+00 WATTS
DC COMPONENT = -3.271441E-05
TOTAL HARMONIC DISTORTION = 6.161156E-03 PERCENT
__________________________________________________
300mV @ 1Khz, 70W pk
TOTAL POWER DISSIPATION 2.51E+00 WATTS
DC COMPONENT = -3.927749E-06
TOTAL HARMONIC DISTORTION = 1.053756E-02 PERCENT
__________________________________________________
400mV @ 1Khz, 124W pk
TOTAL POWER DISSIPATION 2.51E+00 WATTS
DC COMPONENT = -1.381230E-04
TOTAL HARMONIC DISTORTION = 1.244735E-02 PERCENT
__________________________________________________
500mV @ 1Khz, 193W pk
TOTAL POWER DISSIPATION 2.51E+00 WATTS
DC COMPONENT = -2.008052E-05
TOTAL HARMONIC DISTORTION = 1.324213E-02 PERCENT
__________________________________________________
So yeah, depending on the speed of my PC and if I get any more ideas to try out, I might post the circuit tomorrow.
So who's going to make the PCB art??
Cheers
Chris
Hi John,
I realize full well what you say is true, and I do expect the real world circuit rendition to be far worse than simulated, until optimised real world with real equipment and such.
However, I feel since it's far more ideal it should be possible to achieve somewhat ideal results, at least to prove the soundness of the design. Then work out the non idealities real world. Am I wrong there?
What's really bothering me right now is the this. I'm not currently messing with the comparator portion, or the mosfets/driver portion, I'm happy with all that.
So I went back to my four op amp input stage, which I think would simulate alot more accurately than the rest of it.
Just changing a wire connection to a different spot, one that shouldn't change the netlist/circuit flow at all, provides different results. Possibly better, but if worse, obviously I try to change it back, and get different results yet again.
So I'm not sure what to do here. That's how wrong this simulator is.
What I wanted to optimise was the class A biasing of the four op amps. By replacing with 5k resistor with an equivalent current source, the results are far worse when I expect them to be very much the same. Resistors work best.
Changing the resistors to the proper power rail according to Bruno's advice in another thread, provides worse results.
What I've found best is a combination of the first two op amps tied to one rail, and the other two op amps to the opposite rail. Perhaps they induce cancelling currents? It doesn't matter which, I can swap the sets of op amps between rails and both provide great results, but if I tie them both to the positive rail like I should, results suffer too much.
If I tie them both to ground as an "extra" load, results are good.
So none of that makes much sense and what really gets me is that swapping back to the original circuit, does not give the original results!
There is no way I made an error and forgot to change anything back either, because I have the circuit backed up in another folder in case it crashes and locks he file again. Being identical to what I simulated the rest with, it doesn't provide the same results either.
So, I don't want to add a bunch of garbage that makes things look good just because it does, and I didn't think I'd get to a point where spice would be the limiting factor, as far as simple tweaks like that are concerned anyway.
The results aren't all that far off btw, it's basically the difference from THD mostly being in the high 0.00* range or or the current low 0.0*.
I guess from what you're saying and the results it's giving me, there's nothing left worth doing on it in simulation.
Now I have to ask if spice only gets one so far (not very) and equations are much the same story, I guess it's all done with alot of prototyping?
I hope spice isn't so far off that it's all garbage anyway.
I thought since it's essentially computer code it would be consistent with the results, and has been up until now.
Cheers
I realize full well what you say is true, and I do expect the real world circuit rendition to be far worse than simulated, until optimised real world with real equipment and such.
However, I feel since it's far more ideal it should be possible to achieve somewhat ideal results, at least to prove the soundness of the design. Then work out the non idealities real world. Am I wrong there?
What's really bothering me right now is the this. I'm not currently messing with the comparator portion, or the mosfets/driver portion, I'm happy with all that.
So I went back to my four op amp input stage, which I think would simulate alot more accurately than the rest of it.
Just changing a wire connection to a different spot, one that shouldn't change the netlist/circuit flow at all, provides different results. Possibly better, but if worse, obviously I try to change it back, and get different results yet again.
So I'm not sure what to do here. That's how wrong this simulator is.
What I wanted to optimise was the class A biasing of the four op amps. By replacing with 5k resistor with an equivalent current source, the results are far worse when I expect them to be very much the same. Resistors work best.
Changing the resistors to the proper power rail according to Bruno's advice in another thread, provides worse results.
What I've found best is a combination of the first two op amps tied to one rail, and the other two op amps to the opposite rail. Perhaps they induce cancelling currents? It doesn't matter which, I can swap the sets of op amps between rails and both provide great results, but if I tie them both to the positive rail like I should, results suffer too much.
If I tie them both to ground as an "extra" load, results are good.
So none of that makes much sense and what really gets me is that swapping back to the original circuit, does not give the original results!
There is no way I made an error and forgot to change anything back either, because I have the circuit backed up in another folder in case it crashes and locks he file again. Being identical to what I simulated the rest with, it doesn't provide the same results either.
So, I don't want to add a bunch of garbage that makes things look good just because it does, and I didn't think I'd get to a point where spice would be the limiting factor, as far as simple tweaks like that are concerned anyway.
The results aren't all that far off btw, it's basically the difference from THD mostly being in the high 0.00* range or or the current low 0.0*.
I guess from what you're saying and the results it's giving me, there's nothing left worth doing on it in simulation.
Now I have to ask if spice only gets one so far (not very) and equations are much the same story, I guess it's all done with alot of prototyping?
I hope spice isn't so far off that it's all garbage anyway.
I thought since it's essentially computer code it would be consistent with the results, and has been up until now.
Cheers
Welp, I'm done with it.
Here's the results as tested with some class A biasing which I decided was totally unreliable.
It still simulates very well without it, so I'm leaving it out, but according to Bruno's advice on class A biasing an op amp, unless I'm mistaken, a current source (just greater than the output current) should be tied to the positive rail of each op amp to their outputs.
Here's the results as tested with some class A biasing which I decided was totally unreliable.
It still simulates very well without it, so I'm leaving it out, but according to Bruno's advice on class A biasing an op amp, unless I'm mistaken, a current source (just greater than the output current) should be tied to the positive rail of each op amp to their outputs.
Classd4sure:
I belive you'r trying to alter opamps as if they'r running class A with one resistor output to rail or output to gnd. Remember the opa models is different, AND the output current from them coms via gnd not rail. Thats how the modells are made. It is therefore limits abt what and how to simulate.
BSpise- must bee a werry frustrated ekspression.
As a example try to sim a singel opamp (almost any config will do) measuring the output current, this current and bias current will normaly flow in the psu wires. BUT NOT in spice; the output current goes from gnd or sorse gnd to output. Therefore with signal the current to opamps psu are constant but the output current is not. Also this current is only in the psu gnd path and not in the rail part.
You can normaly not sim the Mark Alexander current feedback amp (analog devices) as the current drawn from opamp is proposjonal to the next stage input. So then you will have to make your own sub sircuits.... if...
Also look out for warnings and psu stepping, then there is somthing the pspice is not handling well.
After all spice is there to asisst you, do not make it a trial and error tool.
BTW: Have you tried HIP 4080 ? it is a bridge mos driver that can handle 80V or hi/low driver like hip 2500 ?
(i see my typing and too my self for a bad writing).
Looking forward to see the improowements in the sircuit.
Regards
I belive you'r trying to alter opamps as if they'r running class A with one resistor output to rail or output to gnd. Remember the opa models is different, AND the output current from them coms via gnd not rail. Thats how the modells are made. It is therefore limits abt what and how to simulate.
BSpise- must bee a werry frustrated ekspression.
As a example try to sim a singel opamp (almost any config will do) measuring the output current, this current and bias current will normaly flow in the psu wires. BUT NOT in spice; the output current goes from gnd or sorse gnd to output. Therefore with signal the current to opamps psu are constant but the output current is not. Also this current is only in the psu gnd path and not in the rail part.
You can normaly not sim the Mark Alexander current feedback amp (analog devices) as the current drawn from opamp is proposjonal to the next stage input. So then you will have to make your own sub sircuits.... if...
Also look out for warnings and psu stepping, then there is somthing the pspice is not handling well.
After all spice is there to asisst you, do not make it a trial and error tool.
BTW: Have you tried HIP 4080 ? it is a bridge mos driver that can handle 80V
or hi/low driver like hip 2500 ? (i see my typing and
too my self for a bad writing).Looking forward to see the improowements in the sircuit.
Regards
Hi Konrad,
I had suspected the op amp models might be the cause for the class A biasing not going according to plan, thanks for explaining how that works, I never really studied the various op amp models, I never suspected their operation would be so different.
I still think spice should give the same results at least twice for the same circuit though
I know there's a few bugs with it:
1. Things deleted or moved look like they got deleted/moved but it doesnt' reflect in the netlist, "ghost" parts left behind.
Sometimes copying and pasting the circuit fixes that by forcing a new netlist as I understand, hasn't worked for the last six hours though.
2. It can crash and lock the file from ever being opened again.
3. Before it does crash it gets sloooooooooowwwwwwwwww.
Very frustrating!
I haven't done anything for common mode feedback but, the circuit is posted for ya. Hope ya like it.
Cheers
PS, your typing is just fine, I understand you well, and input is appreciated as always
I had suspected the op amp models might be the cause for the class A biasing not going according to plan, thanks for explaining how that works, I never really studied the various op amp models, I never suspected their operation would be so different.
I still think spice should give the same results at least twice for the same circuit though
I know there's a few bugs with it:
1. Things deleted or moved look like they got deleted/moved but it doesnt' reflect in the netlist, "ghost" parts left behind.
Sometimes copying and pasting the circuit fixes that by forcing a new netlist as I understand, hasn't worked for the last six hours though.
2. It can crash and lock the file from ever being opened again.
3. Before it does crash it gets sloooooooooowwwwwwwwww.
Very frustrating!
I haven't done anything for common mode feedback but, the circuit is posted for ya. Hope ya like it.
Cheers
PS, your typing is just fine, I understand you well, and input is appreciated as always
Hi,
that's my experience with cadence products too, especially with Orcad Capture CIS. "Save early, save often" does not prevent you from having corrupt databases, which cannot be openend again.
One suggestion, coming from other forum members: try LTSpice. It seems to be a lot more stable. Yes, it is a bit more difficult to handle.
Sometimes it helps to create behavioural models for active parts - much faster and you (should) know, what they do. I use this option for comparators as well as for OPAs sometimes, one may add some extra timing specials. I would not rely on the OPA behaviour either, look at their implementation (subcircuit drawing), if available. Sometimes the suppliers define the simulated characteristics.
Timo
that's my experience with cadence products too, especially with Orcad Capture CIS. "Save early, save often" does not prevent you from having corrupt databases, which cannot be openend again.
One suggestion, coming from other forum members: try LTSpice. It seems to be a lot more stable. Yes, it is a bit more difficult to handle.
Sometimes it helps to create behavioural models for active parts - much faster and you (should
) know, what they do. I use this option for comparators as well as for OPAs sometimes, one may add some extra timing specials. I would not rely on the OPA behaviour either, look at their implementation (subcircuit drawing), if available. Sometimes the suppliers define the simulated characteristics.Timo
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