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Class D Switching Power Amplifiers and Power D/A conversion

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Old 20th October 2012, 07:53 AM   #21
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The caps at the drivers were planned like this.

The LED stacking was a correction, because my original clamping at the intput of the IR20957 was slowing down the comparator in a catastrophic way.
I intended to clamp with zener 4V7, but the diode capacities slowed down the comp to bad. The comp out can deliver 15mA and it still took 200ns to charge the diode. So I build the same clamping I used on my earlier breadboard trial, a 5V with 3 LEDs and clamp now with an ordinary 1N4148 against the 5V and a BAS85 against GND. Sloping of the comparator is now around 50ns. Propagation delay also around 50ns. Of course that's not fast, but fast enough and fits to my earlier comparator breadboard. The focus on the comp design is on the jitter noise.
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Old 20th October 2012, 08:26 AM   #22
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...triangle generator and PWM-comparator running.
Rail E-caps, fuses, snubbers....
The way of placing the snubbers is not suited for mass production,
but in DIY, this direct connection is easy to implement and easy to adjust to the optimal resonance frequency for optimized snubbering that also covers the headaches of hard switching.
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Last edited by ChocoHolic; 20th October 2012 at 08:27 AM. Reason: Picture added
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Old 20th October 2012, 10:01 AM   #23
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Now, shows us your bunrt hands
Have you checked electrolutics' max. ripple current? You'll have a lot of it with ~400kHz, +-60V and 10uH.
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Old 20th October 2012, 10:09 AM   #24
Baldin is offline Baldin  Denmark
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Default Kaspar Sinding Meyer, dead?

Great stuff Choco.

Was thinking to investigate the use of better virtual AC ground in self oscillating designs .... but in many designs this is probably not necessary as it is already implemented by the integrator.

Just googled Kaspar Sinding Meyer (Sovadk here on DIY), to find some of his papers (as referred above).... and find this death announcement...
Kaspar Sinding Meyer : Dødsfald - Berlingske Media - Denmark
Hope I'm wrong …. But how many Kaspar Sinding Meyer’s can there be?
Didn't know him directly, but his brilliant work and always sharing mentality, get you to think he was a really good and decent guy.
What a waste
Sorry to sidetrack the subject …

Kind regards Baldin
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Old 20th October 2012, 11:54 AM   #25
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@Adam:
Current ripple in the filter chokes runs -/+ 3.75A peak.
This translates to an e-cap ripple current of 1.53Arms.
The Frolyt ERY 470uF/100V is specified for 1A at 100kHz.
With three of them in parallel we are far inside the SOA, even when we consider an imbalance in the current sharing.

@Baldin:
Here the link to the paper of Kaspar Sinding Meyer of my references.
Academia.edu | Minimizing distortion in self-oscillating switching amplifiers | Kaspar Meyer
I am not sure if he is our Sovadk, also not sure about your link.
In any case your link is pointing to a tragedy of a young guy.
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Old 21st October 2012, 09:35 AM   #26
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Default In Memorial

http://www.dtu.dk/centre/ele/English..._students.aspx

I did not have contact to him in the past, but now I started to read more&more about him and feel really sad that he passed away.
Let's give this thread a one week rest in memorial to Kaspar Sinding Meyer.
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Old 29th October 2012, 02:45 PM   #27
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...fully assembled...
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Old 29th October 2012, 05:14 PM   #28
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looks great!
best part to come
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Old 29th October 2012, 09:20 PM   #29
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Adjustment of gate drive, dead time and snubbers is always an ongoing process.
Here some screen shots of a preliminary, but typical adjustment with a small overlap. All screen shots of this posting are showing the situation in idling situation. Screen shots during hard switching coming soon.

Picture 1: Uce and Ugs of lower MosFet, time base 500ns/Grid
Picture 2: Zoom during turning ON the lower MosFet, time base 50ns/Grid
Picture 3: Zoom during turning OFF the lower MosFet, time base 50ns/Grid

Upper trace: Uce, 50V/Grid (10:1 probe)
Lower trace: Ugs, 5V/Grid (10:1 probe)
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File Type: jpg idle1.JPG (92.2 KB, 297 views)
File Type: jpg idle2.JPG (90.1 KB, 254 views)
File Type: jpg idle3.JPG (97.8 KB, 60 views)
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Old 29th October 2012, 10:08 PM   #30
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A very simple method to examine the details of hard switching is to give zero input signal and connect a load from the amp output to the positive rail and measure on the lower MosFet.
The shown screen shots of the hard switching situation are with 4R7 between amp output and +60V rail.
The load resistor must be a high power device because during the test it will dissipate Vrail^2/R.
Also during hard switching, there should not happen much uncontrolled ringing. This is mostly a question of layout and snubbering.

Picture 1: Zoom during turning ON the lower MosFet, time base 50ns/Grid
Picture 2: Zoom during turning OFF the lower MosFet, time base 50ns/Grid

Upper trace: Uce, 50V/Grid (10:1 probe)
Lower trace: Ugs, 5V/Grid (10:1 probe)
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File Type: jpg hardON.JPG (110.8 KB, 57 views)
File Type: jpg hardOFF.JPG (100.5 KB, 45 views)
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