have you experienced problems with PSRR influencing operationdo you have any waveforms to show us im just curious i like demonstration..
As for your diagram don't snubbing take care of PSRR maybe eva or chocolate man can help you im at the moment working on my output stage mosfet calculations so im a bit caught up with novice level stuff..
Ive dropped the switching frequency to 122Khz using a IRF540N (supplier didn't have IRF540Z in stock)
So at the moment im struggling with two issues:
Mosfet drive calculations.
Switching losses.
IR2011 Gate drive loses
P = Vgs * QG * f
P = 15V * 71 * 10 ^ -9 * 122 * 10 ^ 3
p = 129mW
Gate Drive Current
http://ww1.microchip.com/downloads/en/appnotes/00786a.pdf
Ig = Qg / t( transition time) what is transition time is it the same as the period ?
Dead time is currently set to *50ns* but the mosfets still heat up and the im not sure if the gate drive current is suitable as the 7815 can only source up to *1A*
Are there anything else i need to calculate.. ?
So at the moment im struggling with two issues:
Mosfet drive calculations.
Switching losses.
IR2011 Gate drive loses
P = Vgs * QG * f
P = 15V * 71 * 10 ^ -9 * 122 * 10 ^ 3
p = 129mW
Gate Drive Current
http://ww1.microchip.com/downloads/en/appnotes/00786a.pdf
Ig = Qg / t( transition time) what is transition time is it the same as the period ?
Dead time is currently set to *50ns* but the mosfets still heat up and the im not sure if the gate drive current is suitable as the 7815 can only source up to *1A*
Are there anything else i need to calculate.. ?
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The mosfet gate drive current pulse is very short so the 7815 should be ok.
It lasts as long as it takes to charge up the mosfet gate.
I drive 4 irfb4227's from a 1amp regulator.
I use 105nS deadtime on a irs2092.
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have you experienced problems with PSRR influencing operationdo you have any waveforms to show us im just curious i like demonstration..
As for your diagram don't snubbing take care of PSRR maybe eva or chocolate man can help you im at the moment working on my output stage mosfet calculations so im a bit caught up with novice level stuff..
No I haven't really experienced any big problems. But I'm just wondering how to optimize the circuit and reduce distortion (hopefully making it sound even better), but doing this in an efficient manner.
The bead I'm using now is one with 1k ohm@100 MHz. Think I'll try something like a wirewound 0805 100uH. In class d the most noise will of course be around the resonance freq (e.g 250 kHz) but with broad bands to both sides. Think the bead will actually not be too effecient at these frequences ... probably having an ohmic impedande of 10 ohm .....
Anyway the question was on the influence of PSRR/PSU related noise on distortion.
best regards Baldin
PS. found this ok info on decoupling/bypassing
http://www.designers-guide.org/Design/bypassing.pdf
Gate drive current peaks should come from the corresponding supply decoupling capacitor, not from the regulator. I routinely use a LC filter to derive the gate drive supply of each channel to ensure that these current peaks are confined in a (small) loop formed by the decoupling cap, the driver IC, buffers (if any) and the MOSFET only. If these currents are allowed to flow through bigger-than-needed loops, they can easily cause cross-talk between channels, increased distortion, and erratic behavior at high power. There is cross-talk between adjacent PCB tracks at high frequencies.
I use axial and SMD inductors. Beads don't provide enough attenuation to get the low hash levels I usually aim for in signal supply rails. Inductance has to be high enough to get a cutoff point well below switching frequency with the capacitance dictated by desired high side holdup time (low side capacitance has to be higher, I use 2x high side capacitance to ensure that charging a somewhat drained bootstrap capacitor can't cause low side local rail to drop too much). Too high inductance will result in too low Q in axial inductors, something like 10uH is a good starting point. ESR has to be adequate to prevent resonance with load capacitance. You sound as if you weren't used to designing LC filters to confine HF "hash", which are are needed all the time for clean class D. Simulation of the filter helps a lot.
After some gate drive wiring arrangements including, re-positioning of 10ohm resistor and IN4148 diode at the gate drive and using short wires, the MOSETS started switching hard on/off at +/- 25V @ 132Khz ( The reason nothing was working before was, because of poor layout, vie neatened all wires and paid attention to neatness as much as i can.)
Gate Drive Hi vs Lo from the IR2010 (Notice the ringing)
Eva, vie read in past threads you use a trick using inductor beads at the mosfet gate, to slow and clamp rubbish ringing during switching....
An externally hosted image should be here but it was not working when we last tested it.
Output swing from the power MOSFETS (IRF540N) unloaded. (No snubbing applied)
An externally hosted image should be here but it was not working when we last tested it.
Notice the ringing measured at (20Mhz) probably time to start snubbing...
An externally hosted image should be here but it was not working when we last tested it.
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4 sure snubbing is a good idea.
Besides snubbing also photos of the power stage would give the chance for proposals regarding wiring and positioning of components.
P.S.
When you say unloaded... Does this mean without speaker, or does it mean even without filter?
Hi Chocolate
Some clarity with the loading, no pure resistive load was connected when i took output waveform pictures, and no LPF filter was connected (not that i have one even one prepared yet) its purely showing the mosfet power devices under no load..
However i did manage to connect a pure carbon resistive load (10 ohm, 5 watt) it started to glow, red hot (indicating power transfer into the load) her is the pic of the poor resistor (shame on me for abusing it to this extent
) mosfet warmed up a bit no too much for concern Here is a picture of the scorched resistor
An externally hosted image should be here but it was not working when we last tested it.
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Thanks for the answer.
No I'm not used to design LC filtering on supply lines, and now realise that the beads I'm using are not doing much
.... I chose the best beads I seemed to be able to find 1k@100MHz I think are quite large resistive values as beads goes ... but will not help much at 250 kHz or lower.Probably good I'm not doing this for a living
Not sure it is too common in commercial products to use LC filtering on the different supply lines .... but it is a good idea though
I'll improve my design with coils in the 10 uH range, and will also design this in for the gate drive supply on the next PCB layout
Something like this should do the job Digi-Key - 587-2167-1-ND (Manufacturer - BRL3225T100K)
Best regards Baldin
Ive been spending half a day studying ringing and the effects it has in switching circuits, then some more research around snubbing lots of useful information on the internet however there is still lots to understand around snubbing.. anyway here is the effect i experienced with no snubbing.
20 Mhz ringing peaking with overshot measuring 12Volts
Dramatic improvement almost clean switching achieved with a RC snubber between the drain and source, calculated values are 18nf and a 10 ohm resistor.
(Still evidence of +/- 1Mhz of overshot at about 2 volts)
Ringing from the LO/HO switching node without mosfet snubbing..
Ringing from the LO/HO switching node with mosfet snubbing..
dramatically improved switching dv/dt performance quite a bit
Noticed dead-time set to 60ns, MOSFETS remain frozen cold
20 Mhz ringing peaking with overshot measuring 12Volts
An externally hosted image should be here but it was not working when we last tested it.
Dramatic improvement almost clean switching achieved with a RC snubber between the drain and source, calculated values are 18nf and a 10 ohm resistor.
(Still evidence of +/- 1Mhz of overshot at about 2 volts)
An externally hosted image should be here but it was not working when we last tested it.
Ringing from the LO/HO switching node without mosfet snubbing..
An externally hosted image should be here but it was not working when we last tested it.
Ringing from the LO/HO switching node with mosfet snubbing..
dramatically improved switching dv/dt performance quite a bit
Noticed dead-time set to 60ns, MOSFETS remain frozen cold
An externally hosted image should be here but it was not working when we last tested it.
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This is looking like you would have pretty much inductance in the following loop:
Upper rail - upper Mos - lower Mos - lower rail - rail cap - upper rail
10 Ohms appears more or less reasonable.
18nF... pretty heavy (factor 10-20). Did you calculate the losses in the 10 Ohms considering full supply rail and switching frequency?
Upper rail - upper Mos - lower Mos - lower rail - rail cap - upper rail
10 Ohms appears more or less reasonable.
18nF... pretty heavy (factor 10-20). Did you calculate the losses in the 10 Ohms considering full supply rail and switching frequency?
This is looking like you would have pretty much inductance in the following loop:
Upper rail - upper Mos - lower Mos - lower rail - rail cap - upper rail
10 Ohms appears more or less reasonable.
18nF... pretty heavy (factor 10-20). Did you calculate the losses in the 10 Ohms considering full supply rail and switching frequency?
Hey chocolate vie recalculated snubbed values for C snubber network.
Old snubber network Values
@ 132Khz a 18nf has an impedance of 68.01 ohms (Xc) + 10 ohm fixed = 78ohms..
Rail to Rail 21v + 21v = 42volts switching @ 123Khz.
P = V^2/R 21^2/78 = 6.8watts (to much energy lost) but well damped.
and 12volts 20Mhz ringing 18nf impedance is 0.4ohms + 100 fixed = 100.4ohms
p = 1.4Watts.
New snubber network Values
10nf @ 123Khz = 129ohms + 100 = 229 ohms
Power = 1.9watts.
10nf @ 20Mhz = 0.79ohms + 100 = 100.79 ohms
Power = 1.4watts.
Ive added 100uf decoupling caps the close to the MOSFET supply rails it reduced EMI on the supply quite a bit.
Your loss calculation is little bit oversimplified.
a) The wave shapes are not sinusodial, better simply calculate the losses from traditional resistive cap charging.
b) Z is not the scalar sum of R and Xc, but Z=sqrt(R²+Xc²)
c) There is no need to have a low Xc at the switching f. Xc must be low vs R at the ringing frequency that you want to dampen. If you have 20MHz and a suitful R of 10Ohm, then the Xc at 20MHz shall be in the range around 3 Ohms.
Having a larger C (and consequently lower Xc) also works, but causes more heat without improvement on damping.
Higher art would be to shrink C even further and take the parasitic L into account (adjusting the resonance of the parasitic L and the C to 20MHz).
If done with some love, this allows to reduce the cap (and consequently snubber losses) again about factor 2-3.
But forget that in first step. In your PCB design with lowish 20MHz resonance you would need to build a huge snubber loop in order to get enough parasitic inductance.
First try to get running the traditional RC snubber.
One addon.
Usually you do not start the calculation from the R, but from Coss.
Coss is the output capacitance of the MosFet.
Getting a starting point for the snubber, my personal rule of thumb:
At the ringing frequency we want to have a snubber that brings reasonable damping. For this the Z of the damper should be mostly resistive at the ringing frequency and should be in the same decade range as the Xcoss. Xcoss is the impedance of the output capacitance Coss of the MosFet.
In order to have the Z of the snubber with a similar impedance like Xcoss you can simplify R = Xcoss. In order to get Z mostly resistive you should choose Csnub=3xCoss or sligtly larger, but not excessive.
I guess your ringing became faster since you added the rail caps close to the MosFets.... Pick this frequency, calculate R and C according the rule of thumb above. With this starting point you can go for optimization on the real thing by varying the snubber values and finding the optimum for your set up without suffering from excessive snubber losses.
Usually you do not start the calculation from the R, but from Coss.
Coss is the output capacitance of the MosFet.
Getting a starting point for the snubber, my personal rule of thumb:
At the ringing frequency we want to have a snubber that brings reasonable damping. For this the Z of the damper should be mostly resistive at the ringing frequency and should be in the same decade range as the Xcoss. Xcoss is the impedance of the output capacitance Coss of the MosFet.
In order to have the Z of the snubber with a similar impedance like Xcoss you can simplify R = Xcoss. In order to get Z mostly resistive you should choose Csnub=3xCoss or sligtly larger, but not excessive.
I guess your ringing became faster since you added the rail caps close to the MosFets.... Pick this frequency, calculate R and C according the rule of thumb above. With this starting point you can go for optimization on the real thing by varying the snubber values and finding the optimum for your set up without suffering from excessive snubber losses.
Your loss calculation is little bit oversimplified.
a) The wave shapes are not sinusodial, better simply calculate the losses from traditional resistive cap charging.
b) Z is not the scalar sum of R and Xc, but Z=sqrt(R²+Xc²)
c) There is no need to have a low Xc at the switching f. Xc must be low vs R at the ringing frequency that you want to dampen. If you have 20MHz and a suitful R of 10Ohm, then the Xc at 20MHz shall be in the range around 3 Ohms.
Having a larger C (and consequently lower Xc) also works, but causes more heat without improvement on damping.
Anyways...
Higher art would be to shrink C even further and take the parasitic L into account (adjusting the resonance of the parasitic L and the C to 20MHz).
If done with some love, this allows to reduce the cap (and consequently snubber losses) again about factor 2-3.
But forget that in first step. In your PCB design with lowish 20MHz resonance you would need to build a huge snubber loop in order to get enough parasitic inductance.
First try to get running the traditional RC snubber.
Hey Choc sorry for the late reply vie been busy with other work these few days, also off the topic just purchased a new PICkit-3 from microchip ive been playing around with there new IDE maplab-x IDE
a) The wave shapes are not sinusoidal, better simply calculate the losses from traditional resistive cap charging.,( figured this out later thanks for the heads up)
b) Agreed.
c) Yes, a low value Xc at Fs makes no sense, losses will be excessively high and power delivery in the snubbed "absorber" result in high idle power dissipation.
Research and experiments tell me snubbing is only used as a "patch" and should no be abused like vie done in the past.
Ive also picked up some tricks from the Practical Switching Power Supply Design 1990 Marty Brown.
Here is a another guide from the book
1) Place the scope probe across the node to be snubbed.Take care to minimize any stray pickup that might effect the waveshape by placing the ground lead very close to the element. Then record the peak voltage and the ringing frequency (Fo) of the spike.
2) Place a very small capacitor in parallel with the element terminals to be snubbed.Increase the value of the capacitor until the ringing frequency is cut half of the original unsnubbed ringing frequency.At this point , the value of the parasitic capacitances (Co) will be one-thrid of the paralleled capacitor value.
3) Calculate the estimated optimum value of the snubber's damping resistor by
R = fo * Co / 6.28
4) Place this value resistor in series with the added capacitor.This resistor value may have to be varied one way or the other to yield the desire peak voltage and damping.
Note: The power dissipated within the snubber is given by
Ps = CF * (Vp-p) ^ 2
Where:
C is the snubber capacitance.
F the operating frequency.
Vp-p peak to peak voltage across the snubber capacitor.
Although this approach yields very good results for the snubber values, it may present a problem in power dissipation. A higher value resistor and a smaller value of capacitor will decrease the power within the snubber, but the dampoing factor will worsen and the peak voltage of the spike will grow.
Basically:
The designer must trade off the dissipated power and the peak spike voltage with the purpose of the addition of the snubber.
Be aware of what other areas within the design would be more effective in combatting voltage spikes and RFI generation than adding a clamp or a snubber. They can be viewed as “design patches” for a design weakness or a physical shortcoming of a component. If one is needed, though, the designer should be aware of the factors that indicate the optimum choice and design.
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