High Sample Rate PCM – II
Theory tells us that each time the number of DAC chips is doubled the SNR increases by 3 dB. With 32 chips per channel, we should see a 15 dB increase. That is very good, but we can do better because there is no reason the paralleled DAC chips have to receive identical input data.
In essence, we have a 29-bit DAC for sample rates at or below 768K. For each 24-bit input sample value, we can provide a 29-bit value that produces an output current that is closest to the ideal. Accessing a 16MB look-up table 768K times per second is trivial for a modern 64-bit microprocessor. The table data comes from a one-time calibration procedure that analyses the DAC’s measured output performance for each possible input.
Above 768K, we are dealing with a delta that is obtained by scaling the difference between consecutive samples. Below 11.2896M, two or more chips are paralleled and a table lookup is used to improve accuracy.
In essence, we have a 29-bit DAC for sample rates at or below 768K. For each 24-bit input sample value, we can provide a 29-bit value that produces an output current that is closest to the ideal. Accessing a 16MB look-up table 768K times per second is trivial for a modern 64-bit microprocessor. The table data comes from a one-time calibration procedure that analyses the DAC’s measured output performance for each possible input.
Above 768K, we are dealing with a delta that is obtained by scaling the difference between consecutive samples. Below 11.2896M, two or more chips are paralleled and a table lookup is used to improve accuracy.
Total Comments 2
Comments
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Posted 13th July 2016 at 01:37 AM by abraxalito -
Because the corrections are based on dynamic analysis.
Posted 13th July 2016 at 10:23 PM by Tam Lin