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Old 26th August 2012, 06:12 AM   #271
EUVL is offline EUVL  Europe
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Brad,

> Speaking now of the Constellation-like simplified schematic from JC's post #168:

I spiced essentially the same circuit late last night but use 2SK117, which is essential identical to one half of a 2SK2145.
I use 750R for R3, and 1k for R4 & R5.
Closed loop bandwidth for gain of +2 and -1 are all over 10MHz.
Too much gain at HF. So need a Zobel somewhere.

Only first shot. Some way to go.
Need to get proper models from Toshiba.


Cheers,
Patrick
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Old 26th August 2012, 07:30 AM   #272
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Quote:
Originally Posted by RNMarsh View Post
Great.. what are your ideas?!
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Old 26th August 2012, 12:05 PM   #273
coluke is offline coluke  Italy
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I'm on the Bonsai side (FET only in the input stage, please ), and I'm going to give a try in a few days to this little beast - it is basically a JC-2 with a high current diamond output stage suitable for driving low Z headphones: simulation results are quite good (OLBW > 30 kHz, THD < 0.001% up to 20 kHz @ 100 mW into 30 ohm), and employs fairly standard parts (it happens my drawers are full of 2N3819 and 2N5460 ) - I'll let you know.

Ciao,

L.
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Old 26th August 2012, 12:06 PM   #274
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Quote:
Originally Posted by bcarso View Post
Speaking now of the Constellation-like simplified schematic from JC's post #168:

....one of the problems is that the lower output device must supply all of the input bias current of the upper device, so this intrinsically unbalances the P pair. Throw down a current sink from the output (or just a resistor to the negative rail), then the second stage can be balanced. It's also good to put some voltage drop in the one drain to equalize the drain voltages of the P devices.
....

Now some can argue that the bias resistors could be made larger, but then we run the second stage at lower current, and the input capacitance of the lower N output will slow that section down.

At least, if the two output devices are reasonably well-matched, and perhaps with some ballasting R in the sources, the quiescent bias can be not too unstable.


The proposed source resistors at the output stage are essential for a rugged real life design. Fortunately we are not heading for efficacy and/or excessive output swing, we can easily spend 1V on each source resistor, which will knock down the thermal drift of the output stage reliably and avoids the need of further thermal compensation diodes and thermal couplings with the input stage.
Such source resistors will theoretically increase the output impedance, which is not so much desired, but good for PSRR . Bringing down the output impedance and keeping high PSRR can be done by a I/V resistor at the output (...was somewhere proposed earlier anyway), but most likely increases distortion compared to light load situations.

The intrinsic imbalance can also be reduced by giving the lower Mos a higher source resistor value.
I guess the original usage of that circuit was in an application were the output stage is running at significantly higher currents compared to the driving stage (ref. quasi complentary BJT output stages of power amps).

Regarding the 2nd order distortion struggle between Wavebourne and John, I tend to say that Wavebourne's concerns are basically fitting to the nature of the circuit. The tail which drives the upper output device is operating at massively modulated Vds while the tail which drives the lower output device is operating at low modulation of Vds. Anybody crying for cascoding? No, I would tend to live with it.

Last but not least. I doubt that a simulation with standard models is the right tool to analyze distortions in the sub -80db range.
In my experience the sim helps to find the right direction and see the fundamental nature of the distortions. But in all my past simulate+build trials it turned out that the sim was much nicer than reality.
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Old 26th August 2012, 02:12 PM   #275
Bonsai is offline Bonsai  Taiwan
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Quote:
Originally Posted by coluke View Post
I'm on the Bonsai side (FET only in the input stage, please ), and I'm going to give a try in a few days to this little beast - it is basically a JC-2 with a high current diamond output stage suitable for driving low Z headphones: simulation results are quite good (OLBW > 30 kHz, THD < 0.001% up to 20 kHz @ 100 mW into 30 ohm), and employs fairly standard parts (it happens my drawers are full of 2N3819 and 2N5460 ) - I'll let you know.

Ciao,

L.
Nice :-) I like the general structure, but why are C5 and C6 so high? I would MIC this op-Amp for high slew rate.

There is the opportunity here to go with a single N chan FET LTP (easy to get) rather than the bfully alanced symmetrical.
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Old 26th August 2012, 03:21 PM   #276
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Quote:
Originally Posted by coluke View Post
I'm on the Bonsai side (FET only in the input stage, please ), and I'm going to give a try in a few days to this little beast - it is basically a JC-2 with a high current diamond output stage suitable for driving low Z headphones: simulation results are quite good (OLBW > 30 kHz, THD < 0.001% up to 20 kHz @ 100 mW into 30 ohm), and employs fairly standard parts (it happens my drawers are full of 2N3819 and 2N5460 ) - I'll let you know.

Ciao,

L.
This one gets my vote. It has 10 transistors though.
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Old 26th August 2012, 03:51 PM   #277
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Better fets would be recommended.
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Old 26th August 2012, 03:56 PM   #278
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You could drop it to 8 with just using a couple of complementary to-220 mosfets on the output, instead of the transistor follower.
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Old 26th August 2012, 04:16 PM   #279
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Quote:
Originally Posted by coluke View Post
I'm on the Bonsai side (FET only in the input stage, please ), and I'm going to give a try in a few days to this little beast - it is basically a JC-2 with a high current diamond output stage suitable for driving low Z headphones: simulation results are quite good (OLBW > 30 kHz, THD < 0.001% up to 20 kHz @ 100 mW into 30 ohm), and employs fairly standard parts (it happens my drawers are full of 2N3819 and 2N5460 ) - I'll let you know.

Ciao,

L.
I juiced up the whole thing and distortion is now 0.0005% @ 20kHz into 30 ohms @ 1.1Vrms. DC offset on the output is -1mV.

I have since added Miller capacitors (@10pF each) to get rid of a 15dB spike @ 10MHz. Distortion is now 0.0006% under the above conditions. S/N is 120dB @ 10kHz.

Unfortunately, large heatsinks are required on the outputs.

Finally, something I understand.
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Last edited by dirkwright; 26th August 2012 at 04:18 PM.
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Old 26th August 2012, 05:34 PM   #280
RNMarsh is offline RNMarsh  United States
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Quote:
Originally Posted by dirkwright View Post
I juiced up the whole thing and distortion is now 0.0005% @ 20kHz into 30 ohms @ 1.1Vrms. DC offset on the output is -1mV.

I have since added Miller capacitors (@10pF each) to get rid of a 15dB spike @ 10MHz. Distortion is now 0.0006% under the above conditions. S/N is 120dB @ 10kHz.
:-) how is dc output offset and drift again ?
No coupling caps (10mfd) anywhere and no dc servo?
-RNM

Last edited by RNMarsh; 26th August 2012 at 05:46 PM.
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