I've been a lurker in this thread since it's inception and decided to try my hand at this.
I was wondering if someone could gently outline what sort of tests would be needed to qualify a design that meets the original design goals, in both LTSpice and real-world measurements. Ideally, even a set of LTSpice files with the appropriate tests and maybe even plots, so that we can follow along. For the bench-tests, I think the descriptions can be less verbose.
In order to show this isn't a total troll, I'll post my current progressI'd just like to verify the design before posting details, and would greatly enjoy learning how to do this and not rely on my own presuppositions and self-learned processes.
(In case it's not clear from the photo, which it really isn't, this is a dual opamp with one on each "side". Standard SIP-8 pinout, but I also bring out PSU ground and signal ground (which I don't think is necessary, as it's a differential input circuit))
Beautiful work, you shame me.
Agreed, very nice layout. Would you share the basic topology and output capabilities with us?I've been a lurker in this thread since it's inception and decided to try my hand at this.
I was wondering if someone could gently outline what sort of tests would be needed to qualify a design that meets the original design goals, in both LTSpice and real-world measurements. Ideally, even a set of LTSpice files with the appropriate tests and maybe even plots, so that we can follow along. For the bench-tests, I think the descriptions can be less verbose.
In order to show this isn't a total troll, I'll post my current progress
(In case it's not clear from the photo, which it really isn't, this is a dual opamp with one on each "side". Standard SIP-8 pinout, but I also bring out PSU ground and signal ground (which I don't think is necessary, as it's a differential input circuit))
Dave
At least the usual tests -- General --> THD, FFT, under various output levels and load levels... at least down to 600 Ohms, s/n, PSR, CMR.
Shoot for thd + N of <.001%. Others also >-100db to 20KHz. Max output voltage into 600 to Pro standard level (8v or +22dbv).
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Well I can certainly second (erhh! 3rd) that.
In #2060 FET990, it was a choice between injecting some evil current ala AD797 or losing the advantage of 'pure' Cherry in eliminating xover.
Does Self show the cascode connection in his 5th Ed.? I've tried this in REAL life and found some serious latching & slew problems. Duplicating networks to the mirror works well as in #2060 (and REAL life).
Please post when you find it Brad.
Baxandall describes 2-pole compensation (without TMC, his bastardized Cherry) in his very early WW articles that are now reprinted in Linear Audio's excellent book together with Self's stuff. I used that in an amp after some correspondence when I asked GGB when episode 7 was coming out.
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Should point out the relevance of dis stuff. In many cases, even with supa dupa supplies, it is PSR of the sensitive rail that determines ultimate distortion performance.
This is what I do to LTspice validate #2060 & to compare with SW-OPA.
Distortion via FFT for 20kHz 10Vp into 600R @ 100x gain. This very high gain is used to get the distortion products to a level where we might be able to see them with a good 24b A/D .. above -100dB. Are they low order (good) or loadsa high order stuff which usually means xover (bad)? But so what .. if its all below -100dB
Check stability at 100x 10x & 1x gain using both Transient & AC Analysis. On Transient, analyse at least 10ms as some instability takes a few ms before it shows itself. Have some sort of signal happening eg 20kHz 10Vp.
I'm real suspicious of AC Analysis but I'm a SPICE newbie.
I use 18k + 182 for 100x, 18k + 2k for 10x and either a direct connection between Vo & Vi -ve or 1k. Small cap across the 18k if it helps.
Mild & Severe Overload into those 3 cases. You're looking for clean clipping with no sign of Phase Reversal or latching and 'immediate' recovery. I check for slew on this too as there's not really anything of interest for slew which just reflects the linear HF response. Often instability appears on overload.
You may change your recommendations for compensation caps based on these tests.
The TI app. note TI-an1516.pdf for CMRR & +ve & -ve PSR
I think the PSR tests are useful & valid but IMHO, the CMRR test dun show up important faults.
For this, I do Voltage Follower FFT distortion 3.162Vp 20kHz into 15R. This is seriously head banging so you might want to substitute 10Vp into 600R, 150R etc. It exercises CMR of the input LTP and also shows up xover. Your output device models may complain as will the real life ones.
Check overload too.
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Then I repeat the all above with all the appropriate transistor models at my disposal. it's not quite the same as Monte Carlo or looking at the first production run but it tells my how sensitive the circuit is to device variations.
If you tweak resistors to get 0mV DC offset and the same output Iq, you'll get a feel for how sensitive these adjustments are.
The transistor models from various gurus are in the attached ricardo.txt
#2060 shows how I ring the changes. Thanks to fas42 for this.
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There's a need to check stability with reactive loads eg capacitance from 1n to 100n but I still need to figure out a logical and appropriate test series for this.
BTW, this is all REAL life stuff I do if I'm developing a PA. I don't often do 'new' topologies I haven't tried in REAL life cos I like to have a good handle on whether SPICE is telling porkies.
Don't worry too much if you can't equal SW-OPA in all things. It is after all SOTA. And we all have different priorities. One requirement that Marshy asked for and I agree with .. is a sensible no. of actives.
I might try an even more Jurassic topology to try & reduce the no. of actives.
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Really nice Dunhill.
Don't abandon the separate clean & dirty earths. At the level of SW-OPA, AD797, OPA627, its essential to have a very clear strategy for your earths and decoupling ... otherwise you won't get anywhere near their potential performance.
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There are entry-level smart tweezer DMMs at ~USD 30 or lower. They don't do inductance or voltage, but have both capacitance and resistance to 3000 count resolution. I carry one around to do a quick sanity check for genuine Toshiba (and other) JFETs: Ciss within about /- 25 per cent of the datasheet specs, and nearly identical with S-D reversed. It has already paid for itself several times over with just one purchase of a fractional reel of genuine Toshiba 2sk209-BL.
Search for Mastech MS-8910 or similar.
Seems to be the season. I strung together a mostly-air-circuit to do a quick test of a vacuum tube stage and used a base-current-recycling thing along the lines of Aldridge, with moderately slow bipolars (2SA1015, 2SA1249, running at about 15mA). I tested it with a resistive load to begin with and found that it was rather intolerant of capacitive/transmission-line loading. After some help from base resistors I wound up with about 820 ohms in series with the output collector to make it quit convincingly. It was taking off at about 65MHz.
With a much tighter layout it probably wouldn't require as much series R.
Just completed the layout of a folded Kaneda-style discrete opamp with 7 actives, all currently-available commodity SMDs. Here's the link to the schematic and layout:
http://www.diyaudio.com/forums/analog-line-level/10243-kaneda-preamp-11.html#post3270146
It's about 0.5" x 0.6". Some more space could be saved by using a dual JFET like the 2sk2145, but the singles (2sk209) are easier to source in BL- grade.
Note that it differs from the stock Kaneda - this one is folded, and has rudimentary output stage bias current stabilisation.
http://www.diyaudio.com/forums/analog-line-level/10243-kaneda-preamp-11.html#post3270146
It's about 0.5" x 0.6". Some more space could be saved by using a dual JFET like the 2sk2145, but the singles (2sk209) are easier to source in BL- grade.
Note that it differs from the stock Kaneda - this one is folded, and has rudimentary output stage bias current stabilisation.
This looks very nice, have you tried it in a few of the standard applications to see where it might shine or not? I/V, line amp, pre-amp, input to PA, etc.
I just gave the dual, through-hole version for PCB fabrication today - probably a month for bare PCBs and a week or two after that for assembly and test. I'm hoping it will do OK in line stages in CDPs, DACs, soundcards, etc. - anything with a high-Z load. It could in principle drive low-Z headphones with a heftier output pair and higher output stage bias, though it wasn't designed for that.
Meanwhile, I've upgraded the SMD version to use Rohm IMX2/T2A duals in SC74 packages, which have higher (300 mW) Pd. I'll probably send it out for fabrication only after the through-hole version comes back and passes sanity checks.
In fact this looks to be a little over the top in BW and slew rate. I need to build a tighter prototype since this one seems a little to hot. I just got a little too sloppy on the breadboard. Everything looks great but I can still coax a little fur on the output under some conditions. The basic topology seems to be doing everything intended. I will be piggy-backing some real PC boards over the holiday break on some work projects.
Agreed. I think I'd be more inclined to find something old and contemporary that's in need of some tlc unless some custom deck came up.
Briefly (with properly applied fingers
) at 10kHz, G = 20dB, 500 Ohm load, and 20V p-p the distortion went into the noise. There also does not appear to be any pathological behavior, foldover, supply sticking, etc.Remember this started out for me with the intent of using 140V devices and making a PA front end. The available IC PA front ends are not that great.
And this thread has dragged out a great variety of good discrete device options for all projects.
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