I'm not going argue with that because i never mesaured my speakers... i beleive that they were design to be phase linear but i never trust audio manufacturers...
But if my speakers do have phase shift, it isnt a justification to have another equipment in the audio chain that generate phase shift in the signal...
Best regards
Rick
But if my speakers do have phase shift, it isnt a justification to have another equipment in the audio chain that generate phase shift in the signal...
Best regards
Rick
Hi guys !
One thing: Phaseshift != Phaseshift ! (For nonprogrammers: != means unequal)
If you have constant delay, phasehift linearly increases with freq.
If an amp has constant delay (which would be optimal), it measures
wild phasehifts.
So, the nulltest is somehow nuts, every amplifier has a delay of several
100ns, so the outputsignal is never identical to the inputsignal if
directly compared.
Every speaker has a phaseshift of several ms, depending on where you sit...
A delay can't be audible, it does not modify the signal itself. The only
delay audible would be different delays between channels.
Mike
One thing: Phaseshift != Phaseshift ! (For nonprogrammers: != means unequal)
If you have constant delay, phasehift linearly increases with freq.
If an amp has constant delay (which would be optimal), it measures
wild phasehifts.
So, the nulltest is somehow nuts, every amplifier has a delay of several
100ns, so the outputsignal is never identical to the inputsignal if
directly compared.
Every speaker has a phaseshift of several ms, depending on where you sit...
A delay can't be audible, it does not modify the signal itself. The only
delay audible would be different delays between channels.
Mike
My professors always said that measuring between the + and - inputs of an amp will show the error signal. We all know this. But they also told me that the error signal is the error signal, that nothing can be determined from it; phase, thd, imd, whatever because it's all lumped together and mixed with the noise at such low levels. Were they wrong?
Programming languages are the tyranny of English and mathematical syntax.
The general case is that "!" is short-hand for "not"
So "=" means "equal to", "!=" means "not equal to"
Corruption in the interests of brevity without regard to popular comprehensibility. A little like SMS vernacular.
The general case is that "!" is short-hand for "not"
So "=" means "equal to", "!=" means "not equal to"
Corruption in the interests of brevity without regard to popular comprehensibility. A little like SMS vernacular.
PMA
Agreed.
What I was getting at is that both inputs are supposed to equal. We know this. So, I was taught that what ever difference signal is measured between the inputs is distortion, i.e. the error signal. But, I was also taught that we could not determine what kind of distortion this is. Only that it is distortion. And that was my question. Can the distortion be classified from this error signal?
Agreed.
What I was getting at is that both inputs are supposed to equal. We know this. So, I was taught that what ever difference signal is measured between the inputs is distortion, i.e. the error signal. But, I was also taught that we could not determine what kind of distortion this is. Only that it is distortion. And that was my question. Can the distortion be classified from this error signal?
Re: post 606
To Rodolfo and Andy_C...
I did Andy_C's simulation with LTSpice, and plotted the results as he did originally, but also adding a plot showing the derivative of the two outputs. Ideally this would be flat over the entire transfer region.
This manner of display shows the improvement gained by the complementary feedback pair with much more sensitivity. This is evident in plot number one of the attached PDF file, the BLUE vs. RED traces.
The additional plot tweaks the operating points a bit and subs other transistors in the input of the complementary feedback pair, i.e., as: changed Q1/Q2 to PN4250A and Q18/Q19 to 2N5210, re biased Q1/Q2 to ~100uA. Comparison of this with Andy_C's original shows additional improvements in dynamic range and constancy of gain over the transfer region. This should be evident by comparing the two BLUE curves in the two plots within the PDF.
Andy_C's original simulation made the point that a pair of complementary bipolar feedback pairs arranged in a differential fashion shows more constant transfer gain for large dynamic swings than does a simple degenerated bipolar differential pair. The additional data of the attached plots reinforces this.
Walt Jung
To Rodolfo and Andy_C...
I did Andy_C's simulation with LTSpice, and plotted the results as he did originally, but also adding a plot showing the derivative of the two outputs. Ideally this would be flat over the entire transfer region.
This manner of display shows the improvement gained by the complementary feedback pair with much more sensitivity. This is evident in plot number one of the attached PDF file, the BLUE vs. RED traces.
The additional plot tweaks the operating points a bit and subs other transistors in the input of the complementary feedback pair, i.e., as: changed Q1/Q2 to PN4250A and Q18/Q19 to 2N5210, re biased Q1/Q2 to ~100uA. Comparison of this with Andy_C's original shows additional improvements in dynamic range and constancy of gain over the transfer region. This should be evident by comparing the two BLUE curves in the two plots within the PDF.
Andy_C's original simulation made the point that a pair of complementary bipolar feedback pairs arranged in a differential fashion shows more constant transfer gain for large dynamic swings than does a simple degenerated bipolar differential pair. The additional data of the attached plots reinforces this.
Walt Jung
CFP vs CE
Andy C (or perhaps Walt J?),
would it be possible to ask you to perform an AC and phase sweep anlysis of your circuit posted here?
I think the CFP input stage is indeed a very interesting ciruit.
Walt,
you said that you rebiased Q1/Q2 to 100 uA, in Andys exemple we have 250 uA, are there any other advanatge or drawback with lower bias current for the frontstage transistors in the CFP diff.?
The Fairchild's datasheet I looked at, found here, didn't tell me so much what paremeter change in which direction.
Regards,
Michael
Andy C (or perhaps Walt J?),
would it be possible to ask you to perform an AC and phase sweep anlysis of your circuit posted here?
I think the CFP input stage is indeed a very interesting ciruit.
Walt,
you said that you rebiased Q1/Q2 to 100 uA, in Andys exemple we have 250 uA, are there any other advanatge or drawback with lower bias current for the frontstage transistors in the CFP diff.?
The Fairchild's datasheet I looked at, found here, didn't tell me so much what paremeter change in which direction.
Regards,
Michael
Re: CFP vs CE
Hi Michael,
I don't have much time right now, but I'll mention that the AC analysis I did has some pretty bad peaking in the transconductance above 10 MHz if I recall correctly (actual analysis is at home and I'm at work). I haven't tried Walt's bias change to see how that affects things, nor have I tried tweaking the circuit in any way from the original setup I posted. I hate seeing stuff like that :-(.
Ultima Thule said:
Hi Michael,
I don't have much time right now, but I'll mention that the AC analysis I did has some pretty bad peaking in the transconductance above 10 MHz if I recall correctly (actual analysis is at home and I'm at work). I haven't tried Walt's bias change to see how that affects things, nor have I tried tweaking the circuit in any way from the original setup I posted. I hate seeing stuff like that :-(.
Re: 100mV Line Level
JF,
is that 1V kind of a standard in the industry?
BTW I don't think those "100 mV's" are the issue here, if I understood your issue right , because the voltage difference between + and - input increase with frequency because of several aspects as phase, distortion etc, and thereby the diff stage must cope with larger signal difference nothing to do with the input signal voltage by it's own.
I think still Leach describes this verry well in the link I pointed out in one of my earlier posts.
Pavel,
nice pic's as always from your SpectralLab SW!
What kind of Soundcard etc. do you use for your measurements?
Michael
johnferrier said:
JF,
is that 1V kind of a standard in the industry?
BTW I don't think those "100 mV's" are the issue here, if I understood your issue right , because the voltage difference between + and - input increase with frequency because of several aspects as phase, distortion etc, and thereby the diff stage must cope with larger signal difference nothing to do with the input signal voltage by it's own.
I think still Leach describes this verry well in the link I pointed out in one of my earlier posts.
PMA said:
Pavel,
nice pic's as always from your SpectralLab SW!
What kind of Soundcard etc. do you use for your measurements?
Michael
Michael, I simply dropped the current on the input side based on past experiences with this type of circuit. It improved the linearity, and will also lower the input current.
I will admit to a strong bias to the PN4250As, as they typically run high in beta, and that's a real plus here. Same for the 2N5210, although both are being pushed if you were to really build this for 40V rails. I don't think I'd use either device without a cascode, which would have other benefits.
Many of the Fairchild small signal xstrs are culled from the same process, and it could be that Andy_C's "BC" parts come from the same family as the 2N5210's. This gets hard to pin down, I know. But I do know the PN4250A and 2N5210 to be very high for beta, by measurement, not just from sims.
I'll let Andy_C comment on an addl' sim run. Or, you can download LTSpice and have at it yourself!
Walt Jung
Re: Re: CFP vs CE
10 MHz for the CFP I guess you meant, ok?!
Sorry for asking, I am just not familiar with LTSpice, I used PSpice for 3 years ago the last time and nowdays don't have access to that SW, LTSpice would take too long time, ..at least my curiosity can't wait! Lazy..?
So No hurry Andy..!
andy_c said:
10 MHz for the CFP I guess you meant, ok?!
Sorry for asking, I am just not familiar with LTSpice, I used PSpice for 3 years ago the last time and nowdays don't have access to that SW, LTSpice would take too long time, ..at least my curiosity can't wait! Lazy..?
So No hurry Andy..!
Re: Re: 100mV Line Level
Michael,
this one is measured by Sound Blaster Live! 24bit/96kHz external USB. Only 16 bit resolution used. The FFT noise floor is then
6.02N + 1.76dB + 10log(M/2)
where N is a number of bits and M is a number of samples in the FFT record. For 64k samples, the theoretical noise floor is -143dB. The generator is a special low distortion one developed by a colleague of mine.
Pavel
Ultima Thule said:
Michael,
this one is measured by Sound Blaster Live! 24bit/96kHz external USB. Only 16 bit resolution used. The FFT noise floor is then
6.02N + 1.76dB + 10log(M/2)
where N is a number of bits and M is a number of samples in the FFT record. For 64k samples, the theoretical noise floor is -143dB. The generator is a special low distortion one developed by a colleague of mine.
Pavel
FFT is a narrow band analyze, according to number of samples you analyze noise bandwith of less than 1Hz. Just read the specs of opamps to see what are the numbers related to sqrt(Hz). This is above the range of DIY forum, try to study a bit about FFT. Remember that the graph does not show the rms quantization noise level.
-120dBVrms = 1uVrms
-140dBVrms = 100nVrms
-120dBVrms = 1uVrms
-140dBVrms = 100nVrms
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