Spice and distortion
"Andy,
When you are measuring "distortion" what exactly are you/the simulator measuring? Is it all distortion or a subset like THD?
BAM"
Spice will not give you anywhere near accurate distortion numbers. My eyes roll back in my head in particular when I see people "measuring" for an op amp who Spice model contains only
two transistors with most of rest the model being ideal voltage and current controlled sources.
"Andy,
When you are measuring "distortion" what exactly are you/the simulator measuring? Is it all distortion or a subset like THD?
BAM"
Spice will not give you anywhere near accurate distortion numbers. My eyes roll back in my head in particular when I see people "measuring" for an op amp who Spice model contains only
two transistors with most of rest the model being ideal voltage and current controlled sources.
traderbam said:
I'm only looking at the third harmonic, so it's a pretty limited concept of "distortion". This all started when I read a discussion in the LTSpice user's group on Yahoo about doing Fourier analysis. What people were doing was choosing the time duration of the transient simulation and the number of points in the FFT such that the resulting time step was much smaller than what LTSpice would use if it chose the time steps itself like it does normally. The required time step is then calcuiated by hand and specified as the maximum time step. I do 12 cycles of 20 kHz for a total duration of 6e-4 sec. I choose 65536 points for the FFT, so the time step becomes the oddball value of 9.155273438e-9 sec. Applying this to a simple sine wave source gives the results shown in the plot, with the residual noise about 100 dB down at the third harmonic of a 20 kHz sine wave.
At this point, I'm just trying to figure out the combined contributions of the VAS and input stage. The VCVS shown in my earlier schematics is there to eliminate the loading of the feedback network from the VAS. My original current feedback design had a third harmonic that was only 40 dB down from the fundamental at full power and 20 kHz. With the Slone circuit with collector resistors in the input diff amps, it's about 60 dB down. The feedback factor in this amp is only about 15 dB at 20 kHz, giving a unity loop-gain frequency of a little over 100 kHz. So given this low level of feedback, I'm satisfied with the performance. I don't expect the actual measured performance to correlate very well with this, but it does offer a way of comparing the current feedback and voltage feedback designs.
Attachments
Here is the discussion from the LTSpice user's group that explains setting up the FFT to get minimum spurious outputs. Apologies for the formatting
=============================
--- In LTspice@yahoogroups.com, mathias.borcke@i... wrote:
> Hello *
>
> I want to do distortion analysis in the audio frequency range. This means I
> would like to simulate down to 0.00x percent distortion products.
> Frequently I end up with ca. 1% distortion just measuring the oscillator
> itself.
> The amount of distortion increases with the number of cycles that I
> simulate. (see example circuit below)
> I have made some progress (with a real circuit) with adjusting the
settings
> in the Spice pane of the Control Panel, however I do not really
know what in
> detail these entries mean.
> --> Can you give me a short description of the adjustment options?
> --> Does anyone know a better way to simulate distortion? (DC-transfer
> analysis ?)
>
Hello Mathias
you have to switch off any kind of compression mode in
Control Panel -> Compression . Please click all buttons off.
Next choose a time step of <= 1us, e.g. .TRAN 0 10ms 0 1us.
The result then looks very promising.
I recommend to move the .Fourier statement to its own command line,
otherwise you will not get the comfortable selection box for
the .TRAN statement.
I have attached another thread about fourier analysis with LTSPICE
where I was involved in the past.
Best Regards
Helmut
Attachement:
-----------
"fred bartoli" <toto@h...> schrieb im Newsbeitrag
news:3dd929e8$0$18267$626a54ce@n...
>
> Helmut Sennewald <HelmutSennewald@t...> a écrit dans le
message :
> arb8bm$gl156$1@I...
> >
> > "Piercarlo Boletti" <piercarloboletti@t...> schrieb im
> Newsbeitrag
> > news:1flugn4.1vu8bay1lzya00N%piercarloboletti@t...
> > > Hi!
> > >
> > > I need a little help to understand use of FFT in spice, but
particularly
> > > focused on SwitcherCad-LTspice.
> > >
> > > I use that simulator to esteem intrinsic distortion of a certain number
> > > of basic circuit use in low-frequency or audio application. FFT appear
> > > to be optimal to get a quick glimpse of the overall distortive impact of
> > > the topologies under testing
> > >
> > > BUT
> > >
> > > There is a litte problem with the - or simply my - use of FFT itself.
> > >
> > > More closely: disturbed from costantly too high values of distortion
> > > i've tried a junk meausure of a pure sine generator driving a pure load
> > > resistor. The output expected, a pure fundamental, was not obtained; on
> > > i'ts place was displayed a nastly distorted signal - very distorted
> > > indeed.
> > >
> > > What is wrong?
> >
> > Hello Pierecarlo,
> >
> > when you do discrete Fourier Transform(DFT,FFT), you only take a
> > snapshot from a signal. The discrete Fourier transform then
> > delivers the fourier coeffients of a signal which is equivalent
> > to an infinity number of concatenated snapshots.
> >
> > What do we learn from that?
> > If your snapshot does not contain exactly full periods of all your
> > frequencies(signal), there will be a big discontinuity in the assumed
> > concatenuated signal from one snapshot(window) to the next.
> > As a result, your FFT gives you very broad peaks.
> >
> > That's were the FFT-windows come into play. They force the signal
> > and there derivatives to zero at the ends of your snapshot
(window).
> > This helps but is by far not as good as a well choosen time frame
> > which contains only full periods of your signal.
> >
> > FFT versus DFT
> > --------------
> > The result from the FFT is the same as from the DFT. The only
> > difference is the faster calculation with the FFT. This is
> > especially true when the number of data points is a power of 2.
> > Then a lot of similar calculations can be avoided by the clever
> > FFT algorithm.
> >
> > Resolution and max. frequency
> > -----------------------------
> > The frequency resolution of the DFT is 1/time.
> > If you have a FFT-time of 100ms, you get 10Hz resolution.
> >
> > The max. frquency you get is fmax = 0.5*FFT_data_points/time .
> > Example: time=100ms, data points=16384 -> fmax about 800kHz.
> >
> > Best Result of FFT with SwitcherCADIII
> > --------------------------------------
> > 1. Select .TRAN for exactly a full number of periods of your
> > lowest freuency in the signal.
> > 2. All compression modes off in the menue
> > Tools -> Control Panel -> Compression
> > 3. FFT Settings: Window none
> > Data points; 16384 points or more, depends on up to what
> > frequency you want to look.
> >
> >
> > You will reach sidebands below than -120dB and often they are
> > below -150dB which is more than adequate for your ears.
> >
> >
> > Best Regards
> > Helmut
> >
> >
>
>
> Just one minor adjustment :
> The signal must *not* contain full periods but full periods *minus*
one
> sample time (see what happens at boundaries when connecting the
samples).
> Using full periods leads to some still significant leakages that might hide
> useful details.
Hello Fred,
thank you very much for this correction. It is really important as you said that the last data point in the taken window is not the one which is the first data point of the the next window. This is as more important as less data points we use.
Example with a window of one period and 8 data points.
o o o o
o | | o o
o | | | | o o
o o | | | | | | o o
| | | | | | | |
------------------------------------------------------
0 1 2 3 4 5 6 7
The whole thing is a bit more complicated due to the .TRAN analysis
which is normally set to another timestep then used by the FFT.
SwitcherCADIII then has to nterpolate the data points used for the
FFT.
Hey, a great idea came into my mind.
Select the time step for simulation to span/16384 for a intended
FFT with 16384 data points. The time step looked very odd,
but the result has been impressive. Now I have achieved -180dB !!!
spurious signal level for a pure sine source. Thanks Mike too for
the high numerical precision.
> One way to deal with that is to apply windowing to ensure both extremity of
> the curve will nicely join but this still leads to some leakages. This also
> apply only in the case you can post process the waveform, and I
don't know
> whether SWCad can do that or not.
>
> The other way is, provided you anticipate the FFT number of points,
to set
> the total simulation time to
> N*SigPeriod*(1-1/(2*FFTDataPoints)) i.e. N*SigPeriod - 1 sample
time
>
> Also let enough time for the transients to settle i.e. provide a
non null
> start recording time to the .TRAN
>
I agree, this is the next pitfall, because we always have bandwidth limiting elements (C, L) which lead to startup transients in the .TRAN simulation.
Best Regards
Helmut
=============================
--- In LTspice@yahoogroups.com, mathias.borcke@i... wrote:
> Hello *
>
> I want to do distortion analysis in the audio frequency range. This means I
> would like to simulate down to 0.00x percent distortion products.
> Frequently I end up with ca. 1% distortion just measuring the oscillator
> itself.
> The amount of distortion increases with the number of cycles that I
> simulate. (see example circuit below)
> I have made some progress (with a real circuit) with adjusting the
settings
> in the Spice pane of the Control Panel, however I do not really
know what in
> detail these entries mean.
> --> Can you give me a short description of the adjustment options?
> --> Does anyone know a better way to simulate distortion? (DC-transfer
> analysis ?)
>
Hello Mathias
you have to switch off any kind of compression mode in
Control Panel -> Compression . Please click all buttons off.
Next choose a time step of <= 1us, e.g. .TRAN 0 10ms 0 1us.
The result then looks very promising.
I recommend to move the .Fourier statement to its own command line,
otherwise you will not get the comfortable selection box for
the .TRAN statement.
I have attached another thread about fourier analysis with LTSPICE
where I was involved in the past.
Best Regards
Helmut
Attachement:
-----------
"fred bartoli" <toto@h...> schrieb im Newsbeitrag
news:3dd929e8$0$18267$626a54ce@n...
>
> Helmut Sennewald <HelmutSennewald@t...> a écrit dans le
message :
> arb8bm$gl156$1@I...
> >
> > "Piercarlo Boletti" <piercarloboletti@t...> schrieb im
> Newsbeitrag
> > news:1flugn4.1vu8bay1lzya00N%piercarloboletti@t...
> > > Hi!
> > >
> > > I need a little help to understand use of FFT in spice, but
particularly
> > > focused on SwitcherCad-LTspice.
> > >
> > > I use that simulator to esteem intrinsic distortion of a certain number
> > > of basic circuit use in low-frequency or audio application. FFT appear
> > > to be optimal to get a quick glimpse of the overall distortive impact of
> > > the topologies under testing
> > >
> > > BUT
> > >
> > > There is a litte problem with the - or simply my - use of FFT itself.
> > >
> > > More closely: disturbed from costantly too high values of distortion
> > > i've tried a junk meausure of a pure sine generator driving a pure load
> > > resistor. The output expected, a pure fundamental, was not obtained; on
> > > i'ts place was displayed a nastly distorted signal - very distorted
> > > indeed.
> > >
> > > What is wrong?
> >
> > Hello Pierecarlo,
> >
> > when you do discrete Fourier Transform(DFT,FFT), you only take a
> > snapshot from a signal. The discrete Fourier transform then
> > delivers the fourier coeffients of a signal which is equivalent
> > to an infinity number of concatenated snapshots.
> >
> > What do we learn from that?
> > If your snapshot does not contain exactly full periods of all your
> > frequencies(signal), there will be a big discontinuity in the assumed
> > concatenuated signal from one snapshot(window) to the next.
> > As a result, your FFT gives you very broad peaks.
> >
> > That's were the FFT-windows come into play. They force the signal
> > and there derivatives to zero at the ends of your snapshot
(window).
> > This helps but is by far not as good as a well choosen time frame
> > which contains only full periods of your signal.
> >
> > FFT versus DFT
> > --------------
> > The result from the FFT is the same as from the DFT. The only
> > difference is the faster calculation with the FFT. This is
> > especially true when the number of data points is a power of 2.
> > Then a lot of similar calculations can be avoided by the clever
> > FFT algorithm.
> >
> > Resolution and max. frequency
> > -----------------------------
> > The frequency resolution of the DFT is 1/time.
> > If you have a FFT-time of 100ms, you get 10Hz resolution.
> >
> > The max. frquency you get is fmax = 0.5*FFT_data_points/time .
> > Example: time=100ms, data points=16384 -> fmax about 800kHz.
> >
> > Best Result of FFT with SwitcherCADIII
> > --------------------------------------
> > 1. Select .TRAN for exactly a full number of periods of your
> > lowest freuency in the signal.
> > 2. All compression modes off in the menue
> > Tools -> Control Panel -> Compression
> > 3. FFT Settings: Window none
> > Data points; 16384 points or more, depends on up to what
> > frequency you want to look.
> >
> >
> > You will reach sidebands below than -120dB and often they are
> > below -150dB which is more than adequate for your ears.
> >
> >
> > Best Regards
> > Helmut
> >
> >
>
>
> Just one minor adjustment :
> The signal must *not* contain full periods but full periods *minus*
one
> sample time (see what happens at boundaries when connecting the
samples).
> Using full periods leads to some still significant leakages that might hide
> useful details.
Hello Fred,
thank you very much for this correction. It is really important as you said that the last data point in the taken window is not the one which is the first data point of the the next window. This is as more important as less data points we use.
Example with a window of one period and 8 data points.
o o o o
o | | o o
o | | | | o o
o o | | | | | | o o
| | | | | | | |
------------------------------------------------------
0 1 2 3 4 5 6 7
The whole thing is a bit more complicated due to the .TRAN analysis
which is normally set to another timestep then used by the FFT.
SwitcherCADIII then has to nterpolate the data points used for the
FFT.
Hey, a great idea came into my mind.
Select the time step for simulation to span/16384 for a intended
FFT with 16384 data points. The time step looked very odd,
but the result has been impressive. Now I have achieved -180dB !!!
spurious signal level for a pure sine source. Thanks Mike too for
the high numerical precision.
> One way to deal with that is to apply windowing to ensure both extremity of
> the curve will nicely join but this still leads to some leakages. This also
> apply only in the case you can post process the waveform, and I
don't know
> whether SWCad can do that or not.
>
> The other way is, provided you anticipate the FFT number of points,
to set
> the total simulation time to
> N*SigPeriod*(1-1/(2*FFTDataPoints)) i.e. N*SigPeriod - 1 sample
time
>
> Also let enough time for the transients to settle i.e. provide a
non null
> start recording time to the .TRAN
>
I agree, this is the next pitfall, because we always have bandwidth limiting elements (C, L) which lead to startup transients in the .TRAN simulation.
Best Regards
Helmut
no need for current mirrors with complementary input stage
I'll admit that it would be interesting to see a solution to the original problem of how to combine complementary LTP input stages with current mirrors, but look at it this way:
The main function of the current mirror is to double the open loop gain. You can also get that extra gain by using a second input pair. The part count penalty is exactly one transistor: the current source for the second LTP. If you really want a good mirro, you should be using matched transistors, and you might as well employ them as the second input pair. You'd need a PNP current source in the VAS anyway, so you might as well drive it actively (no extra cost, except that the PNP should now be as fast as the NPN type). So it boils down to the extra current source transitor for the second LTP, and some will argue that a resistor should be used here anyway. OK, and if you are cascoding the input stage, then there is another two exta small signal transistors.
What are the advantages of complementary vs. single ended+mirror?
- less delay in the input stage, therefore less compensation necessary and hence more open loop bandwidth
- cancellation of even order distortion
What is the downside?
- The current mirror keeps the LTP balanced. So without a current mirror. careful calculation of all bias points is needed + generous degeneration to avoid drift as a function of temperature. I think I have seen a servo loop someplace that acts to balance the LTP. Will have to go digging.
Regards,
Eric
I'll admit that it would be interesting to see a solution to the original problem of how to combine complementary LTP input stages with current mirrors, but look at it this way:
The main function of the current mirror is to double the open loop gain. You can also get that extra gain by using a second input pair. The part count penalty is exactly one transistor: the current source for the second LTP. If you really want a good mirro, you should be using matched transistors, and you might as well employ them as the second input pair. You'd need a PNP current source in the VAS anyway, so you might as well drive it actively (no extra cost, except that the PNP should now be as fast as the NPN type). So it boils down to the extra current source transitor for the second LTP, and some will argue that a resistor should be used here anyway. OK, and if you are cascoding the input stage, then there is another two exta small signal transistors.
What are the advantages of complementary vs. single ended+mirror?
- less delay in the input stage, therefore less compensation necessary and hence more open loop bandwidth
- cancellation of even order distortion
What is the downside?
- The current mirror keeps the LTP balanced. So without a current mirror. careful calculation of all bias points is needed + generous degeneration to avoid drift as a function of temperature. I think I have seen a servo loop someplace that acts to balance the LTP. Will have to go digging.
Regards,
Eric
Yes it does. I'm not sure this is the "main function" that designers seek when using one. More commonly it is to improve CMRR and large signal linearity. After all the open loop gain can be increased easily by increasing the bias current or by reducing the miller capacitance.
What do you mean by "less delay in the input stage"?
Cancellation of distortion depends entiely on the exact matching of the non-linearities of the mirrored transistors. Finding exact matches between pnp and npn is extremely challenging. If they are not exactly matched you simply increase distortion by doubling the number of devices in the signal path.
Re: Slone Amplifier
Rob,
His email address doesn't seem to be mentioned in his book anywhere. I can't seem to find it on the web either. Do you have it?
I've also found that the potential problem with oscillation of the VAS pointed out by mikek in:
http://www.diyaudio.com/forums/showthread.php?postid=195641#post195641
is showing up in simulations as well. For the transistors specified in Slone's design it seems stable, but after substituting very simliar transistors it is not. This leads me to believe that the margin of stability of this VAS stage is very low. In addition to abandoning the current mirror design idea, I've abandoned the 3-transistor VAS as well, and instead gone with a simple cascode VAS like the Opti-MOS design has. It looks like the Opti-MOS design isn't susceptible to any of these problems. So if anyone is thinking of building any Slone designs, the Opti-MOS looks like the safest bet.
weinstro said:
Rob,
His email address doesn't seem to be mentioned in his book anywhere. I can't seem to find it on the web either. Do you have it?
I've also found that the potential problem with oscillation of the VAS pointed out by mikek in:
http://www.diyaudio.com/forums/showthread.php?postid=195641#post195641
is showing up in simulations as well. For the transistors specified in Slone's design it seems stable, but after substituting very simliar transistors it is not. This leads me to believe that the margin of stability of this VAS stage is very low. In addition to abandoning the current mirror design idea, I've abandoned the 3-transistor VAS as well, and instead gone with a simple cascode VAS like the Opti-MOS design has. It looks like the Opti-MOS design isn't susceptible to any of these problems. So if anyone is thinking of building any Slone designs, the Opti-MOS looks like the safest bet.
traderbam said:
I simulated a few input stages with load resistors our current mirrors, and to my surprise, there was always a small delay for the current source version.
Cancellation: Compare a single-ended VAS with a load current source, which is asymmetric and hence has significant k2, k4, ..., to a complentary version with two VAS transistors in push-pull mode. In first order approximation, the second VAS has the same asymmetry, but it is mirrored, so the two will cancel. In reality, this happens only to the degree that they are the same, but getting rid of 2/3 of even order distortion is already nice, isn't it?
A similar thing goes on in the input stages.
Regards,
Eric
Actually, I have built several push-pull amps and have been listening to the final version for many years, and from time to time I have compared it to commercial amps I had in for repair, or to simpler (single LTP and single-ended VAS) amps I sometimes make for friends, and I found these uninspired and slightly blurry.
My theory is that second order disto has a masking effect on third order disto, and removing 2nd while allowing a significant amont of uneven orders to remain may sound more unpleasant than the original signal.
Last not least, 2nd order disto is euphonic in itself, hence the interest in Pass amps, Vifa/Scan ring radiators and Scan slit membrane midwoofers.
Regards,
Eric
My theory is that second order disto has a masking effect on third order disto, and removing 2nd while allowing a significant amont of uneven orders to remain may sound more unpleasant than the original signal.
Last not least, 2nd order disto is euphonic in itself, hence the interest in Pass amps, Vifa/Scan ring radiators and Scan slit membrane midwoofers.
Regards,
Eric
three new ideas to combine symmetrical input stage and current mirrors
Over in the "subjective effects of topology" thread, jcx suggested a current servo scheme which is probably hard to implement.
Lukas then suggested putting a floating current source between the two VAS collectors. This looks surprisingly easy and simple! OK, if it is a JFET source, it is probably not a very good current source, but it should be sufficient to force both VAS transistors into a reasonably stable operating point, especially if some emitter degeneration can be used. HF issues can be overcome by bridging the floating current source with a cap. The problem remains, however, that the current source will have a voltage drop, and that it will have to sit on one side of the bias generator, therefore introducing a lower rail compliance to one side. Comments?
Another approach that came to me last night is to use inverted cascodes, i.e. for a NPN input pair, you would use PNP rather than NPN cascode transistors (and vice versa for the PNP input pair). This way, the voltage at the VAS bases relative to the rails would be defined, but probably some emitter generation on the VAS would be needed to reduce drift. If you want to maintain the AC gain of the VAS, however, you can always bridge these with a cap.
Regards,
Eric
Over in the "subjective effects of topology" thread, jcx suggested a current servo scheme which is probably hard to implement.
Lukas then suggested putting a floating current source between the two VAS collectors. This looks surprisingly easy and simple! OK, if it is a JFET source, it is probably not a very good current source, but it should be sufficient to force both VAS transistors into a reasonably stable operating point, especially if some emitter degeneration can be used. HF issues can be overcome by bridging the floating current source with a cap. The problem remains, however, that the current source will have a voltage drop, and that it will have to sit on one side of the bias generator, therefore introducing a lower rail compliance to one side. Comments?
Another approach that came to me last night is to use inverted cascodes, i.e. for a NPN input pair, you would use PNP rather than NPN cascode transistors (and vice versa for the PNP input pair). This way, the voltage at the VAS bases relative to the rails would be defined, but probably some emitter generation on the VAS would be needed to reduce drift. If you want to maintain the AC gain of the VAS, however, you can always bridge these with a cap.
Regards,
Eric
capslock said:
Here's another one - stick current sources in teh VAS emitters, but you'd of course need higher rails for the VASes thant the diff amps..... But that would increase their emitter impedances, dropping gain, so you'd have to bypas teh curent sources.
Gets too complex for me, so I'm not sure that I want to pursue it.
Has someone tested the ideias above?
I simulated the slone circuit and found the same trouble. Then I found this thread... and some ideas to solve the prblem, with no answers. In order to not reinvent the wheel, I would like to know if someone has reached a conclusion about the circuit and its stability.
The circuit looks promising. But with this kind of iq variation it has no use.
I simulated the slone circuit and found the same trouble. Then I found this thread... and some ideas to solve the prblem, with no answers. In order to not reinvent the wheel, I would like to know if someone has reached a conclusion about the circuit and its stability.
The circuit looks promising. But with this kind of iq variation it has no use.
Re: no need for current mirrors with complementary input stage
Actually the solution has existed for nearly 20 years...courtesy of linsle-hood. However, his approach results in a rather low open-loop gain...distortion is not exactly awe-inspiring.....
While the current mirror does double the open-loop gain over a that obtainable from a simple resistive load, i suggest that in audio applications anyway, its main raison d'etre is to force nominaly equality of diff. stage quiescent currents, and therefore enhance the integrity of input and feedback signal subtraction.
You cannot achieve this doubling in open-loop gain by merely using complementary diff. stages with resistive loads...all things being equal of course...
The only advantages of a fully complementary gain-block over the ubiquitous current-mirrored Thompson topology, are:
- symmetrical psrr
-nominally symmetrical slew
-ahhhh....
...that it....
capslock said:
Actually the solution has existed for nearly 20 years...courtesy of linsle-hood. However, his approach results in a rather low open-loop gain...distortion is not exactly awe-inspiring.....
capslock said:
While the current mirror does double the open-loop gain over a that obtainable from a simple resistive load, i suggest that in audio applications anyway, its main raison d'etre is to force nominaly equality of diff. stage quiescent currents, and therefore enhance the integrity of input and feedback signal subtraction.
You cannot achieve this doubling in open-loop gain by merely using complementary diff. stages with resistive loads...all things being equal of course...
capslock said:
The only advantages of a fully complementary gain-block over the ubiquitous current-mirrored Thompson topology, are:
- symmetrical psrr
-nominally symmetrical slew
-ahhhh....
...that it....
Hi MikeK
Thanks for your reply.. I have done some simulations so far, without the mirrors at input, with bad results... the open loop gain problably is low, and THD is high.. I haven´t tried yat the CCS in the VAS. Has anyone tired to put it, to see the results, obvioluly disregarding the complexity that arises.
In fact, the Lin topology is more straigh-forward to implement, and, despite the problems with assymmetrical slew rates , it gave excellent results, with the corrections as stated by Self.
JY
Thanks for your reply.. I have done some simulations so far, without the mirrors at input, with bad results... the open loop gain problably is low, and THD is high.. I haven´t tried yat the CCS in the VAS. Has anyone tired to put it, to see the results, obvioluly disregarding the complexity that arises.
In fact, the Lin topology is more straigh-forward to implement, and, despite the problems with assymmetrical slew rates , it gave excellent results, with the corrections as stated by Self.
JY
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