"State-Of-MOS": 200W Ultra Low Distortion Pure FET Amplifier

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It depends on the practical amount of local feedback capacitance. If values are chosen too low it will not stabilize. For example, the 47pF's along the output transistors don't do a thing in simulation - the OT parasitic inductances are not modelled. However, the 47pf comes from experimentally determining the proper amount of capacitance to "shut up" OT local oscillations. This method allows for very small gate stoppers, which in turn allows the OPS to be fast enough to be included in the compensation loop. The same goes for the 10pF's along the driver pair and the cascode feedback caps along the IRFs in the VAS rail. When these are dimensioned properly, Cdom (100pF) should determine whether there'll be global oscillation or not. 100pF at least in the sim is more than sufficient, it could go as low as ~50 - 60pF but then the amp won't always stabilize well below that.

Edit: looping back Cdom from the OPS output rather than VAS output yields a significant distortion improvement.
 
Edit: looping back Cdom from the OPS output rather than VAS output yields a significant distortion improvement.

Indeed, but most people that have tried it in practice found it oscillates. Perhaps not in your case, since you state the output stage is very fast (it will need to be).

In practice, do C4-C7 really allow you to use 18 ohm gate resistors? In my experience (with dual-die Exicon devices) at least a few hundred ohms is necessary to overcome the negative input impedance.

Good luck with the building and testing.
 
Yeah, those caps between drain and gate allow such low gate stoppers in practice; the 80W amp I talked about is using such configuration 100% stable. Without the caps, there would be oscillation of around 80MHz. 47pF appeared to be enough to get the parasitic oscillation to shut up. That amp is playing music as we 'speak' :)
 
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I think Erno Borbely invented tracking cascode (If I understand tracking cascode is the one keeping constant Vds on lower device). I was using such cascodes in discrete opamps by Erno (I was using LEDs for this type of biasing - because I was unable to find devices with high enough Vgs). Here we can see great way to set custom Vds and keep it constant in the simple way and here is the great way for high voltage stages. What is more this is pretty straight forward to implement and really scale able.
Great design!

The earliest implementations I could find of tracking cascodes was by the Japanese although I admit Im not sure who devised it.

Maybe you didnt fully understand my post, I was refering to the cascode on the vas circuit. Now that is new, wouldnt you say ............
 
Yeah, right :rolleyes:

Do you even know how that vas is operating and what the benefits are.
Perhaps show us some implementions in audio.........



my point is simply as stated, i don't know enough about the function of the amp to say if its original or not, only to say that it very rarely is. clever? very likely and if truly original, steps should be taken to leverage that or the OP will regret it when someone else makes a bundle

are you really that much of a goose? did you even read my post on the previous page stating for all to see that i didn't understand enough the function of the amp? so your attempt to belittle is moot :D and pretty boring, byee
 
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psst.. no need to get riled up, let's just discuss the amp and its sections.. :) Meanwhile I've converted the last ideal CCS into discretes and it didn't impact figures noticably. Sub ppm numbers at those power levels I can no longer achieve, however, the figures are still between 1 and 2 ppm which I think is great. I've tried all kinds of things to further improve sections but it's moot - no changes lead to a path that noticably improves performance - save trying different transistor models. I guess I ran into a brick wall with the given circuit structure.
 
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my point is simply as stated, i don't know enough about the function of the amp to say if its original or not, only to say that it very rarely is

are you really that much of a goose? did you even read my post on the previous page stating for all to see that i didn't understand enough the function of the amp? so your attempt to belittle is moot:D and pretty boring, byee

Are you ??

I didnt make any attempt to belittle anyone, just pointing out that "nothing new under the sun" is not quite correct. You guys need to lighten up, why so touchy.
 
Regarding tracking cascode look here.
http://www.diyaudio.com/forums/solid-state/182554-thermaltrak-tmc-amp-3.html#post2643498
It is a bit different as the cascode bias current does not flow to the LTP tail.
It was suggested by Bob Cordell here. From Bob explanation you can see why is better that way.
http://www.diyaudio.com/forums/soli...lls-power-amplifier-book-155.html#post2494814
This amp plays music already.
dado

Interesting series of posts, in my scematic it would be just an additional FET to achieve the same result. I'll see if that causes any improvements.. :) Since the bias CCS is practically not loaded at all, save the cascode gates I doubt it will bring additional improvements but it's worth a try.
 
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so the facetious attitude is par for the course? maybe thats just you i dunno. not riled up, just paying back in kind. i'll pop back when the amp is built, its very intriguing either way.

Well kudos to you too mate.

What facetious attitude, I dont quite understand what youre on about so Ill leave it at that.

Anyway the design is much more interesting than where these posts are leading, dont you think ?? So lets rather pay attention to the design and see how a build goes.
 
cascodes are practically insensitive to Vref noise - it is a non-problem

but shorting "upper" and "input" gates together with added C does defeat the cascode action - Miller multiplied Cgd current is then seen the input device gate
 
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Hi jcx,

I've looked at it , but apparently I'm not using the cascode to reduce the Miller effect, rather to provide for a higher voltage. Your comment made me think though, and so I removed the ZVP4424 and just had the IRF sit there, with its local compensation, driven by the source follower. Distortion figures became worse over the previous setup. I think the benefit still comes from the nullified miller capacitance of the ZVP4424 (Vds remains pretty much constant). The miller capacitance of the IRF itself seems to have no effect on slope.

It might be interesting to analyse the particular setup in greater detail and figure out the exact benefits.

P.S. bypassing the resistors in the IPS cascodes definitely help against distortion as they act as a buffer to keep the gates affixed irregardless of small fluctuations in the bias current running through the resistors.
 
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