This is my HDCD digital filter box.
first version
I used a little extruded case that I bought on eBay.
Hammond Mfg. 1455L1201BK
first version
I used a little extruded case that I bought on eBay.
Hammond Mfg. 1455L1201BK
An externally hosted image should be here but it was not working when we last tested it.
picture from the back
I'm using a little 4.5 watt wall wart power supply
first version
I'm using a little 4.5 watt wall wart power supply
first version
An externally hosted image should be here but it was not working when we last tested it.
PCB bottom picture
113 surface mount resistors on the PCB bottom side. All digital signals are impedance controlled, The circuit board is a 4 layer-board with a full ground plane inside on layer 2. The third layer is filled with five seperate planes for all the power supplies.
Flooded ground areas on the top and bottom.
113 surface mount resistors on the PCB bottom side. All digital signals are impedance controlled, The circuit board is a 4 layer-board with a full ground plane inside on layer 2. The third layer is filled with five seperate planes for all the power supplies.
Flooded ground areas on the top and bottom.
An externally hosted image should be here but it was not working when we last tested it.
bare PCB picture
An externally hosted image should be here but it was not working when we last tested it.
PARTS
top picture
1. CS8416 SPDIF receiver with two coax inputs.
2. Altera EPM7064S.
3. JTAG port used to flash the Altera.
4. PMD100 HDCD chip.
5. Channel button.
6. Channel indicators
7. Scale button.
8. Scale, ERROR, HDCD, >48K indicators
9. 74ACT2229 dual FIFO.
10. PIC16F677 Controller.
11. Chassis Ground terminal for static protection.
12. CS8406 SPDIF transmitter and coax output.
13. 74AHCT157 mux.
14. Transformer isolated I/O.
An externally hosted image should be here but it was not working when we last tested it.
top picture
1. CS8416 SPDIF receiver with two coax inputs.
2. Altera EPM7064S.
3. JTAG port used to flash the Altera.
4. PMD100 HDCD chip.
5. Channel button.
6. Channel indicators
7. Scale button.
8. Scale, ERROR, HDCD, >48K indicators
9. 74ACT2229 dual FIFO.
10. PIC16F677 Controller.
11. Chassis Ground terminal for static protection.
12. CS8406 SPDIF transmitter and coax output.
13. 74AHCT157 mux.
14. Transformer isolated I/O.
Theory of operation
The CS8416 SPDIF receiver with two coax inputs will receive up to 192K.
The Altera EPM7064S provides all the glue logic between receiver, PMD100, FIFO, and transmitter. The only exception is the master clock from the receiver goes to both Altera and transmitter with impedance controlled traces.
I bought the PMD100 HDCD chip on eBay and it was shipped in from Asia. I have it set to oversample 2X. Therefore, 44.1K data input becomes 88.2K data output.
The Scale button will manipulate pin 19 of the PMD100. I also provided jumpers in case I decide I don't need a scale button and want to leave it set a certain way.
The 74ACT2229 FIFO has two channels 512 bits deep. After the receiver locks on to a SPDIF stream, the FIFO will come out of reset and the PMD100 will begin to clock in sets of 24 bit data words into the FIFOs.
Once the FIFOs get half full, the Altera controller will begin to clock out and assemble a left-justified data stream for the transmitter.
The data gets clocked from PMD100 into the FIFO pair with 24 bit clocks, left and right at the same time. The data gets clocked out of the FIFOs with 24 clocks for the left, 8 zeros inserted, 24 clocks for the right, and 8 more zeros inserted. The FIFO stays approximately half full with about 10 or 11 samples rippling through at any time. The Altera generates an appropriate bit clock and word clock for the output data stream.
The PIC16F677 Controller resets the box and sets up the PMD100, and controls the front panel buttons and lights. She also holds in EEPROM a bit for the current channel and a SCALE bit for each channel. These 3 EEPROM bits will restore the box to prior settings at power on.
The 74AHCT157 mux bypasses the PMD100 when the received data stream is greater than 48K.
The CS8406 SPDIF transmitter uses the 256x received data clock. When the input data is 48K or less and the PMD100 is upsampling 2X, the CS8406 has HWCK0 set for 128X clock.
If the input data stream changes to above 48K, the processor sets the mux to bypass the PMD100, set the CS8406 HWCK0 to 256X clock, and give a quick reset to the CS8406 to make the change.
If the input data stream goes back to 48K or less, the processor sets the mux to the FIFO outputs, set the CS8406 HWCK0 back to 128X clock, and give a quick reset to clear the FIFO and CS8406 to make the change.
The processor also controls the PMD hard mute input in case the channel or scale button gets pushed, recieve lock is lost, or data input is >48K.
The CS8416 SPDIF receiver with two coax inputs will receive up to 192K.
The Altera EPM7064S provides all the glue logic between receiver, PMD100, FIFO, and transmitter. The only exception is the master clock from the receiver goes to both Altera and transmitter with impedance controlled traces.
I bought the PMD100 HDCD chip on eBay and it was shipped in from Asia. I have it set to oversample 2X. Therefore, 44.1K data input becomes 88.2K data output.
The Scale button will manipulate pin 19 of the PMD100. I also provided jumpers in case I decide I don't need a scale button and want to leave it set a certain way.
The 74ACT2229 FIFO has two channels 512 bits deep. After the receiver locks on to a SPDIF stream, the FIFO will come out of reset and the PMD100 will begin to clock in sets of 24 bit data words into the FIFOs.
Once the FIFOs get half full, the Altera controller will begin to clock out and assemble a left-justified data stream for the transmitter.
The data gets clocked from PMD100 into the FIFO pair with 24 bit clocks, left and right at the same time. The data gets clocked out of the FIFOs with 24 clocks for the left, 8 zeros inserted, 24 clocks for the right, and 8 more zeros inserted. The FIFO stays approximately half full with about 10 or 11 samples rippling through at any time. The Altera generates an appropriate bit clock and word clock for the output data stream.
The PIC16F677 Controller resets the box and sets up the PMD100, and controls the front panel buttons and lights. She also holds in EEPROM a bit for the current channel and a SCALE bit for each channel. These 3 EEPROM bits will restore the box to prior settings at power on.
The 74AHCT157 mux bypasses the PMD100 when the received data stream is greater than 48K.
The CS8406 SPDIF transmitter uses the 256x received data clock. When the input data is 48K or less and the PMD100 is upsampling 2X, the CS8406 has HWCK0 set for 128X clock.
If the input data stream changes to above 48K, the processor sets the mux to bypass the PMD100, set the CS8406 HWCK0 to 256X clock, and give a quick reset to the CS8406 to make the change.
If the input data stream goes back to 48K or less, the processor sets the mux to the FIFO outputs, set the CS8406 HWCK0 back to 128X clock, and give a quick reset to clear the FIFO and CS8406 to make the change.
The processor also controls the PMD hard mute input in case the channel or scale button gets pushed, recieve lock is lost, or data input is >48K.
second version. I built up the second PCB and soldered the HDCD chip in without using a socket.
22uF MLCC ceramic caps, 6V3 X7R, are soldered directly to the power pins. thanks to carlosfm for the tip to reduce the noise on the PMD-100.
22uF MLCC ceramic caps, 6V3 X7R, are soldered directly to the power pins. thanks to carlosfm for the tip to reduce the noise on the PMD-100.
An externally hosted image should be here but it was not working when we last tested it.
The second version has BNC connectors instead of RCA jacks.
(RG-187 courtesy of Jocko)
I also added 13000uF of capacitance to improve the hold-up time through power line glitches.
I am happy with the sound.
(RG-187 courtesy of Jocko)
I also added 13000uF of capacitance to improve the hold-up time through power line glitches.
I am happy with the sound.
An externally hosted image should be here but it was not working when we last tested it.
I designed and ordered custom front panel and rear panel from frontpanelexpress.com
An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
Thanks for posting. Very well made.
I have a PMD100. But, ahem, its not exactly as well made. They sound great don't they?
Why are you only running at 2x? Surely you want to run it in 8x
If you're running off a wall wart, I guess you have the advantage of a seperate transformer, but do you find your regulation good enough? I see you have a lot of decoupling going on. I guess its enough due to the seperate power supply and the isolation SPDIF can give you.
I like the decoupling on the actual chip pins. Did you notice a difference after this was implemented?
Mine's only in stand alone mode. I'd quite like to implement a PIC to drive it one day.
I have a PMD100. But, ahem, its not exactly as well made. They sound great don't they?
Why are you only running at 2x? Surely you want to run it in 8x
If you're running off a wall wart, I guess you have the advantage of a seperate transformer, but do you find your regulation good enough? I see you have a lot of decoupling going on. I guess its enough due to the seperate power supply and the isolation SPDIF can give you.
I like the decoupling on the actual chip pins. Did you notice a difference after this was implemented?
Mine's only in stand alone mode. I'd quite like to implement a PIC to drive it one day.
Hi Phil, thanks for your comments.
2x mode converts 44100 to 88200. 8x is over 352K samples, which is too fast for SPDIF and the usual transmitter and receiver chips. 2x mode also makes the timing easy for the FIFO and the Altera logic. 88200 can be recieved by most DACs built in the last decade or so.
I'm using a 9V wall wart, then L-R-C filtering using 13000 uF caps, then regulating to 5V and 3V3 supplies. It's good enough.
The box is drawing 235mA from the 9V supply. A mains transformer and supply would cost a lot and easily double the size of the box.
The PMD-100 HDCD chip is very noisy without the 1206 ceramic X7R soldered directly to the power pins. I recommend that anyone using the chip make that modification, it will improve the sound of your DAC or whatever you are using it. It makes a big difference.
2x mode converts 44100 to 88200. 8x is over 352K samples, which is too fast for SPDIF and the usual transmitter and receiver chips. 2x mode also makes the timing easy for the FIFO and the Altera logic. 88200 can be recieved by most DACs built in the last decade or so.
I'm using a 9V wall wart, then L-R-C filtering using 13000 uF caps, then regulating to 5V and 3V3 supplies. It's good enough.
The box is drawing 235mA from the 9V supply. A mains transformer and supply would cost a lot and easily double the size of the box.
The PMD-100 HDCD chip is very noisy without the 1206 ceramic X7R soldered directly to the power pins. I recommend that anyone using the chip make that modification, it will improve the sound of your DAC or whatever you are using it. It makes a big difference.
HDCD Equipment Approval Procedure
hello rossl,
I saw your unit, it's very cool one!
In particular, I think you choice 2X oversampling is very nice idea. Because you can evade the weak point of 3stage cascading oversampling digital filter like PMD100.
By the way I would like to you 3 questions.
In 1996, Pacific Microsonics, Inc released to HDCD licencer, "HDCD Equipment Approval Procedure Sheet".
In this sheet, there are some guidance of function testing method.
Now I have this sheet, but now PMI sold HDCD business to Microsoft.
My Questions
1) Do you know Microsoft member who submits this documents?
2) Do you want this document?
3) Do you want HDCD logo mark?
hello rossl,
I saw your unit, it's very cool one!
In particular, I think you choice 2X oversampling is very nice idea. Because you can evade the weak point of 3stage cascading oversampling digital filter like PMD100.
By the way I would like to you 3 questions.
In 1996, Pacific Microsonics, Inc released to HDCD licencer, "HDCD Equipment Approval Procedure Sheet".
In this sheet, there are some guidance of function testing method.
Now I have this sheet, but now PMI sold HDCD business to Microsoft.
My Questions
1) Do you know Microsoft member who submits this documents?
2) Do you want this document?
3) Do you want HDCD logo mark?
Attachments
Hi nagaesan,
At this time I don't plan on selling the unit, so I did not bother with the license procedure.
I bought the PMD-100 on Ebay, and the original purchaser of the IC must have had a license, so PMD must have received the licensing fee at that time. That is why I also did not use the official HDCD logo.
I would like to see the document and logo. Do you have it in PDF form, or is it on paper?
Thanks, Ross L.
At this time I don't plan on selling the unit, so I did not bother with the license procedure.
I bought the PMD-100 on Ebay, and the original purchaser of the IC must have had a license, so PMD must have received the licensing fee at that time. That is why I also did not use the official HDCD logo.
I would like to see the document and logo. Do you have it in PDF form, or is it on paper?
Thanks, Ross L.
The person wanting documents please e-mail it to me.
I attach a pdf file, please make entry of your e-mail address.
After having obtained documents, writing necessary matter, let's perform license application.
However, I do not know the person in charge of Microsoft.
Please teach me, if you know Microsoft person.
I attach a pdf file, please make entry of your e-mail address.
After having obtained documents, writing necessary matter, let's perform license application.
However, I do not know the person in charge of Microsoft.
Please teach me, if you know Microsoft person.
Attachments
Hi nagaesan,
I am violating 2.1. of the licensing agreement that requires redbook CD data to be supressed by 6db. The scale button on my unit allows the user to either comply with the requirement or to turn off the "scale" and violate the licensing.
I have found that the requirment is not necessary and its only purpose is to make HDCD material artifically sound better. After several weeks of listening, I find there is no advantage to turning scale "on" and making the unit comply with 2.1. of the licensing agreement.
Turning on the scale lowers the signal of Redbook CDs by 6dB and lowers it closer to the noise floor of the listening system. This is unnecessary.
HDCD material, after being decompressed by the decoder, will have an average of lower overall volume. This is easily compensated by turning up the volume control. The higher dynamic range clearly makes these recordings better than Redbook and there is no technical need to artifically depress the Redbook data.
regards,
Ross L.
I am violating 2.1. of the licensing agreement that requires redbook CD data to be supressed by 6db. The scale button on my unit allows the user to either comply with the requirement or to turn off the "scale" and violate the licensing.
I have found that the requirment is not necessary and its only purpose is to make HDCD material artifically sound better. After several weeks of listening, I find there is no advantage to turning scale "on" and making the unit comply with 2.1. of the licensing agreement.
Turning on the scale lowers the signal of Redbook CDs by 6dB and lowers it closer to the noise floor of the listening system. This is unnecessary.
HDCD material, after being decompressed by the decoder, will have an average of lower overall volume. This is easily compensated by turning up the volume control. The higher dynamic range clearly makes these recordings better than Redbook and there is no technical need to artifically depress the Redbook data.
regards,
Ross L.
Digital Attenuation of PMD100 [Gainscale & Overall scaling]
Hi! rossl,
HDCD licencee wants same output voltage, when playback Linear PCM and Non Linear PCM [HDCD's Peak Extention] .
If a sound is small, we hear a sound badly. And if sound level is difference, we must controll volume, it is troublesome.
I know you do not want using PMD100's Gainscale function [Digital Domain -6dB] because always you want using fullscall of DAC-IC.
But, PMI forgives "Gainscaling function with analog stage".
For example, in case of MarkLevinson No.30.5L, this was Analog Gainscaling. No.30.5L had a Gainscaling infomation output.
This is No.5 pin[GAIN] output, and connect to MarkLevinson's pre-amplifier.
But in the case of me, I am using Digital Gainscaling.
D/A converter unit is DAC-1.5 of The Parts Connection.
The original DAC-1.5 is fixed No.5[GAIN] and No.19[SCAL] position.
I also want using DAC fullscale, but I don't want level changing when playback PCM/HDCD.
So I attached GAIN/SCAL switch on the rear panel.
By the way, do you know "full-scale output level" is difference" PMD100 and SM5842AP?
Please check "fullscale" square waveform on TEST CD with your cool HDCD decording unit.
Hi! rossl,
HDCD licencee wants same output voltage, when playback Linear PCM and Non Linear PCM [HDCD's Peak Extention] .
If a sound is small, we hear a sound badly. And if sound level is difference, we must controll volume, it is troublesome.
I know you do not want using PMD100's Gainscale function [Digital Domain -6dB] because always you want using fullscall of DAC-IC.
But, PMI forgives "Gainscaling function with analog stage".
For example, in case of MarkLevinson No.30.5L, this was Analog Gainscaling. No.30.5L had a Gainscaling infomation output.
This is No.5 pin[GAIN] output, and connect to MarkLevinson's pre-amplifier.
But in the case of me, I am using Digital Gainscaling.
D/A converter unit is DAC-1.5 of The Parts Connection.
The original DAC-1.5 is fixed No.5[GAIN] and No.19[SCAL] position.
I also want using DAC fullscale, but I don't want level changing when playback PCM/HDCD.
So I attached GAIN/SCAL switch on the rear panel.
By the way, do you know "full-scale output level" is difference" PMD100 and SM5842AP?
Please check "fullscale" square waveform on TEST CD with your cool HDCD decording unit.
Attachments
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