Spice simulation

[Bob Cordell]

An unpleasant surprize

Call me a whiner, but I've got a beef.

This weekend I was evaluating some OnSemi ThermalTrak devices. As part of my investigation, I wanted to run some Gummel plots up to a couple of amps. So that I could keep heating to a minimum, I went to attach the device to a heatsink. Low and behold, the darn hole in the part is just a smidge too small for a 6-32 screw. Go figure. What were they thinking? (Metric?). I just drilled the sucker out a smidge, but what an extra pain!

BTW, the OnSemi SPICE model appears to stink in regard to modeling Vbe vs IC (that doesn't mean SPICE is not tremendously useful!).

The good news is that the real P and N devices match REALLY well in both Beta and Vbe. For those interested, the thermal tracking diode has the same junction drop as the transistor when it is conducting about 1/4 the collector current of the transistor.

Cheers,
Bob

 

[LineSource]

For anyone desiring to simulate Bob Cordell's ThermalTrak circuits, andy_c developed improved Spice models for On-Semi Qmjl3281 and Qmjl1302. These models have given me good results with LTSPICE.

I would appreciate Spice models for any of the large Sanken Bipolar output devices, especially the
2SA1215Y 2SC2921Y
2SA1216G 2SC2922G


You can find more details on andy_c thread.

.MODEL Qmjl3281a_mod npn
+IS=6.5498e-11 BF=139.247 NF=1.00176 VAF=46.776
+IKF=10 ISE=7.75232e-12 NE=3.34341 BR=4.98985
+NR=1.09511 VAR=4.32026 IKR=4.37516 ISC=3.25e-13
+NC=3.96875 RB=11.988 IRB=0.111742 RBM=0.102914
+RE=0.00127227 RC=0.209833 XTB=0.115253 XTI=1.03146
+EG=1.11986 CJE=1.0531e-08 VJE=0.4 MJE=0.450375
+TF=2.6464e-9 XTF=1000 VTF=2.06045 ITF=175
+CJC=5e-10 VJC=0.4 MJC=0.85 XCJC=0.959922
+FC=0.1 CJS=0 VJS=0.75 MJS=0.5
+TR=1e-07 PTF=0 KF=0 AF=1


.MODEL Qmjl1302a_mod pnp
+IS=3.25053e-12 BF=60.3363 NF=0.992063 VAF=19.8199
+IKF=7.18352 ISE=3.25712e-12 NE=3.42487 BR=5.15499
+NR=1.03617 VAR=2.77936 IKR=9.38159 ISC=2.5e-13
+NC=3.89405 RB=0.776136 IRB=0.0998107 RBM=0.776136
+RE=0.000613663 RC=0.0424163 XTB=1.43773 XTI=1
+EG=1.05 CJE=1.0690e-08 VJE=0.728073 MJE=0.42161
+TF=2.9458e-9e-09 XTF=1000 VTF=4.11586 ITF=380
+CJC=1.79861e-09 VJC=0.814822 MJC=0.473271 XCJC=1
+FC=0.8 CJS=0 VJS=0.75 MJS=0.5
+TR=1e-07 PTF=0 KF=0 AF=1

 

[JPV]

I am very pleased to see that the T topology is considered as optimal for the output stage.
This is not what J.Curl told me in his post 406 ??

Having read the different posts and opinions on biasing and gm doubling I am giving hereunder a summary of HP Oliver paper on the subject. This paper has some typo’s errors making it difficult to read (IMHO) therefore I tried to clarify it.
This development clarifies the matter, shows how much ‘the old wise guys’ are correct but raises ( IMHO) some questions.

Calculation of Ro output resistance of a push pull stage in function of total current
(See annexed drawing)
Re emitter resistor
Rb source and base resistor
R half resistance referred to the emitter (emitter base bias loop)
= Rb/(beta+1) + Re
Io bias current
Io+i1 total current in collector of transistor 1
Io+i2 total current in collector of transistor 2
e Thevenin output test voltage
i= i2-i1 test current
Ro output resistance with vin = 0
2Vo bias voltage
Vt thermal voltage kT/q
gm trans-conductance of one transistor at Io

Procedure:

Find i1 and i2 function of e
Calculate R1 = -de/di1 ( minus sign because e is increasing with i1 decreasing which gives a negative derivative)
Calculate R2 = de/di2
Ro = R1//R2
Plot Ro in function of i with Re as parameter

An easier way is to plot gmÄRo where ÄRo is the difference between Ro at crossover (i=o) and Ro at large signal and this with gmR as parameter. The multiplication by gm normalizes ÄRo and then gmÄRo is a number without dimension. This is plotted as second drawing in the attached file.

Calculation

R= Rs /(1+â) + Re

By KLV

Vt ln(1+ (Io+ i1 )/Is) + R(Io+ i1) = Vo – e (1)
Vt ln( 1+(Io+ i2 )/Is) + R(Io+ i2) = Vo + e (2)

At idle e= i = 0
Vt ln( 1+(Io/Is)) + R(Io) = Vo

Replacing Vo in (1) gives and executing:
Vtln(Is+Io+ i1) –VtlnIs +RIo + Ri1 = RIo –VtlnIs +Vtln(Is+Io) - e

Neglecting Is and dividing both sides by Vt gives with gm = Io/Vt:

Ln(1+ i1/Io) + gmR (i1/Io) = -e/Vt (3)
Ln(1+ i2/Io) + gmR (i2/Io) = e/Vt (4)

For each value of i2 e is found by (4) and i1 is found by solving (3) by successive approximation numerically.
The result gives numerically e function of i1 and i2 or i

We can now calculate Ro or better gmRo

gmRo = gmR1//gmR2 with

gmR1 = -gmde/di1 = gmR + 1/(1+ i1/Io) using dln(1+ax)/dx = a/1+ax
gmR2 = gmde/di2 = gmR + 1/(1+ i2/Io)

Estimation of Ro at crossover and for large signal

At crossover i=e=0 = i1 = i2
R1=R + 1/gm
R2=R + 1/gm and Ro = R/2 + 1/2gm

If i2/Io is very large then R2 = R and Io+ i1 = 0 because T1 is cut off , then i1 / Io =-1
And R1 is infinite which make sense
Then Ro= R2=R Ro=R

We can now plot in function of i/Io gmÄRo = gm(Ro – R) the normalized difference between Ro and Ro at large signal. This plot gives the variation of Ro with signal for different values of gmR

The conclusion is:

The key parameter for biasing is the product gmR
For i large then Ro = R
For i = 0 then R0 = R/2 + 1/2gm

If gmR<1
Then Ro increases with i decreasing

If gmR=1
Then Ro stays constant with i except for a small bump at i= about 4Io

If gmR>1
Then Ro decreases with i decreasing except for a bump at i = 4Io where it increases

The Gm of the stage is =1/Ro because the voltage forward gain (( Vo/Vin) for iout =0 )of this quadripole is 1
The voltage gain is RL/(Ro+RL) RL being the load. Variation in Gm with iout gives distortion.
Depending on gmR, the stage Gm will decrease or increase.
Gm can only increase with i decreasing if gmR>1. In this case Ro comes close to R/2 halving therefore Gm doubles. This is in the no realistic case of gmR very large. A better sentence would be : Gm increasing and not doubling
In this way, Leach is more or less right but his Spice simulation is misleading because he made it with Rgm=1. Of course then you will see no variation in the plot of the voltage gain, the bump being to small to be seen.

As M. Curl is saying, the best is to bias at Rgm=1, drive with a voltage source and use many output transistors in //, this makes class A operation larger and the bump in Ro decreases because //. Also the bump appears at a rather large power in the load making it less audible.

Two remarks:
The influence of the source Rb is obvious and makes in some cases the concept of critical biasing ( gmR=1) not realistic.

If gmR=1 is pertinent, then this should remain constant with temperature which means that gm should remain constant with temperature and not Io in the biasing scheme. This is dangerous but could perhaps be well implemented with Thermaltrak transistors.

What do you think?

JPV

 

[john curl]

Chas, to be exact, it would seem to me that we would have to include higher order distortion (especially 7th harmonic) weighting. Has anyone done this with Spice?

 

[Charles Hansen]

Chas, to be exact, it would seem to me that we would have to include higher order distortion (especially 7th harmonic) weighting. Has anyone done this with Spice?

Self's book has some nice graphs that shows voltage gain of the output stage versus voltage swing at the output. Ideally this would be a horizontal line. Sharp kinks mean high-order harmonics. Asymmetry from left-to-right means even-ordered distortion.

With MicroCap (even the the free eval version), you can let it run multiple sweeps while stepping the value of the emitter resistors. It is pretty obvious which resistor value is best for a given bias voltage (or vice-versa).

 

[Bob Cordell]

Gee, Charles, you and I are on the same page. What a concept!

Actually, I think Charles is about three chapters ahead:

1. He has made successful product with vertical MOSFETs.

2. He is using ThermalTrak BJT's, which overcome significant problems with BJTs.

3. He uses SPICE.

Cheers,
Bob

 

[andy_c]

Self's book has some nice graphs that shows voltage gain of the output stage versus voltage swing at the output. Ideally this would be a horizontal line. Sharp kinks mean high-order harmonics. Asymmetry from left-to-right means even-ordered distortion.

Hi Charles,

There's an interesting thing about the "kinks" in the FET SPICE plots.

The Oliver paper deals with output stage nonlinearity in terms of the variation of the output impedance with current, while Self looks at the variation of voltage gain in a similar way - taking the derivative of Vout with respect to Vin. What I like about Oliver's approach is that it removes the load from consideration. Back in post 555 on page 23 of this thread I did some plots where I swept a DC current source at the output of a complementary EF and SF and plotted the derivative of the output voltage with respect to the swept current. This was to show the incremental low-frequency output impedance vs. current. If you look at the one for the FET, you'll see the "kinks". It's clear that the slope of the simulated output impedance is discontinuous in two places. Since the output impedance itself is defined as a slope, then it's a "slope of the slope" or second derivative phenomenon.

Let's look at the second derivative of the Id-Vgs equations that SPICE uses in the simple FET model (in this case, level 1). The equations are:

Id = 0 for Vgs < Vto
Id = K(Vgs - Vto)² for Vgs >= Vto

So for Vgs < Vto, the second derivative is 0. But for Vgs >= Vto, the second derivative is 2K. There's a discontinuity in the second derivative of Id vs. Vgs at Vgs = Vto. A reasonable hypothesis might be that the discontinuity in the second derivative of Id vs. Vgs is causing a discontinuity in the second derivative of Vout vs Iout. This is equivalent to a discontinuity in the slope of the output impedance vs. output current.

How can we test this hypothesis? Well, the BSIM3 FET SPICE model has equations for Id vs. Vgs for which all the derivatives are continuous (reference here). Also, Edmond Stuart (estuart) has created subcircuit models for the 2SJ201 and 2SK1530 that use the BSIM3 FET model internally. If we take my circuit from the post on page 23 and replace the FETs with Edmond's models, we can look at the output impedance vs. current. I have done so, adjusting the bias for 150 mA per device. I've plotted the output impedance vs. current using the same scale as the plots on page 23. I've attached the plot below. Notice there are no kinks at all, and the plot is indeed very smooth.

So my conclusion is that the kinky behavior of the FET SPICE plots (both in Self's book and on page 23 of this thread) is due to a deficiency in the level 1 SPICE models and not the devices themselves. BSIM3 seems to fix this.

 

[john curl]

Fellow designers, let me give you a short history of my experience with power amps that might clarify the situation.
In the 1970's I designed a small power amp that was single sided called the JC-3 that became the ML-2 in order that I not receive any royalties. This is a well known product that was single sided, BUT it became unreliable with power supply voltages over +/- 25V because of the dreaded second breakdown known to all amp designers as an evil in power transistors.
For a more powerful amplifier, I switched over to the balanced bridge output design in order to make a 250W/channel power amp for Gale Electronics in London, in 1975-76. This design was superficially similar to what Charles makes today, except that I used negative feedback, slower output devices, (that's all that Motorola made at the time) choke input power supply, stepped power supply, only a complementary Darlington configuration, instead of a triple Darlington. However, Charles I used the FAMED NEC complementary V-fets that you seem to like on the input, (until they pulled the plug on the manufacture of them), and I achieved 100V/us slew rate. The prototype is last owned by Ira Gale.
Then in 1977, I designed a 100W/channel bridged power amp for Symmetry, that also used a bridge configuration, and it sounded better, because it used faster and more linear Motorola complementary output transistors. The point that is important here is that my PRIMARY protection for the output stages was a CIRCUIT BREAKER, not an elaborate V-I scheme, electronic crowbar, or plain fuse. This prototype is owned by Noel Lee
Because of my success with this technique, I moved on in 1980 to make a 250W bridged amp with ring emitter transistors that had a slew rate over 1000V/us and CIRCUIT BREAKER protection only. Once again, the circuit breaker beat the output devices in limiting the current. Brian Cheney of VMPS owns this prototype.
Then in 1984, I thought that I could make a 100W amplifier with Vmosfets that only took a single side. In other words, I could go from the +/- 25V to +/- 40V for the bipolars to +/- 45V for a single sided Vmosfet output stage using 100V devices.
I made the prototype, and it worked well and sounded great, EXCEPT that a simple circuit breaker would NOT protect it from shorts.
What to do? Faster circuit breaker? That was expensive. Bigger output devices? I tried the 140 devices, and I still had problems. Paralleled bigger output devices? Better, but not perfect, and finally I was working on advanced V-I protection when the stock market crash of 1987, made our company fall into the ocean, and that was the end of that.
In 1989, I started working as a consultant for Parasound. They had a design (from the Toshiba handbook) that was similar to what I normally designed, and they wanted some help with it. This design had a PROVEN V-I protection circuit that allowed single sided operation with fair amounts of power such as 100-250W without any problem, except for the output relay that was a necessary component in this scheme. Still, it worked then, and it still works today. We have pushed the voltage from +/- 60V in the early days to +/- 90V today, all because of that protection scheme.
Is it perfect? NO WAY! But it is a good solution, especially when you want high power and reasonably low cost.
Each one of these designs has been made without extensive Spice sumulation. What a concept! Some people don't even need calculators, (but I am not one of them)
Now, Bob thinks that I did something wrong in my initial Vmosfet design. I haven't found any evidence yet that I made a real mistake, just that I believed the designers data sheet a little too literally, and Vmosfets were not as safe from V-I problems as they implied.

 

[john curl]

Were's the Spice simulation? Just kidding!

 

[jan.didden]

Fellow designers, let me give you a short history of my experience with power amps that might clarify the situation.
In the 1970's I designed a small power amp that was single sided called the JC-3 that became the ML-2 in order that I not receive any royalties. This is a well known product that was single sided, BUT it became unreliable with power supply voltages over +/- 25V because of the dreaded second breakdown known to all amp designers as an evil in power transistors.
For a more powerful amplifier, I switched over to the balanced bridge output design in order to make a 250W/channel power amp for Gale Electronics in London, in 1975-76. This design was superficially similar to what Charles makes today, except that I used negative feedback, slower output devices, (that's all that Motorola made at the time) choke input power supply, stepped power supply, only a complementary Darlington configuration, instead of a triple Darlington. However, Charles I used the FAMED NEC complementary V-fets that you seem to like on the input, (until they pulled the plug on the manufacture of them), and I achieved 100V/us slew rate. The prototype is last owned by Ira Gale.
Then in 1977, I designed a 100W/channel bridged power amp for Symmetry, that also used a bridge configuration, and it sounded better, because it used faster and more linear Motorola complementary output transistors. The point that is important here is that my PRIMARY protection for the output stages was a CIRCUIT BREAKER, not an elaborate V-I scheme, electronic crowbar, or plain fuse. This prototype is owned by Noel Lee
Because of my success with this technique, I moved on in 1980 to make a 250W bridged amp with ring emitter transistors that had a slew rate over 1000V/us and CIRCUIT BREAKER protection only. Once again, the circuit breaker beat the output devices in limiting the current. Brian Cheney of VMPS owns this prototype.
Then in 1984, I thought that I could make a 100W amplifier with Vmosfets that only took a single side. In other words, I could go from the +/- 25V to +/- 40V for the bipolars to +/- 45V for a single sided Vmosfet output stage using 100V devices.
I made the prototype, and it worked well and sounded great, EXCEPT that a simple circuit breaker would NOT protect it from shorts.
What to do? Faster circuit breaker? That was expensive. Bigger output devices? I tried the 140 devices, and I still had problems. Paralleled bigger output devices? Better, but not perfect, and finally I was working on advanced V-I protection when the stock market crash of 1987, made our company fall into the ocean, and that was the end of that.
In 1989, I started working as a consultant for Parasound. They had a design (from the Toshiba handbook) that was similar to what I normally designed, and they wanted some help with it. This design had a PROVEN V-I protection circuit that allowed single sided operation with fair amounts of power such as 100-250W without any problem, except for the output relay that was a necessary component in this scheme. Still, it worked then, and it still works today. We have pushed the voltage from +/- 60V in the early days to +/- 90V today, all because of that protection scheme.
Is it perfect? NO WAY! But it is a good solution, especially when you want high power and reasonably low cost.
Each one of these designs has been made without extensive Spice sumulation. What a concept! Some people don't even need calculators, (but I am not one of them)
Now, Bob thinks that I did something wrong in my initial Vmosfet design. I haven't found any evidence yet that I made a real mistake, just that I believed the designers data sheet a little too literally, and Vmosfets were not as safe from V-I problems as they implied.

John,

Great story. I always find it fascinating to read about how you guys, accomplished designers, get ahead step by step.

I have one question though. At a certain point you decided that the bridged approach with the circuit breaker was not (or no longer) satisfactory and you switched to single ended design and all the accompanying issues for the V/I protection. (If I read you correctly). Why did you make the switch in the first place?

Jan Didden

 

[Charles Hansen]

As explained above, the assertion that a positive value of beta will always lead to latchup is wrong. If you believe in the equation G = A/(1-A*B), then this must be so. If you don't believe in this equation, then your beef is with Mr. Black, not me.

As I explained above, your interpretation of the behavior of the equation G = A/(1-A*B) and the behavior of the system as a function of Beta is simply not right.

I'm trying to hang in there, I really am. But so far you haven't convinced me. There are a couple of problems. The first is that it's not at all clear to me that your equation applies in this instance. Just like SPICE, we are trying to make a mathematical construct that reflects the real world. And then instead of actually having to build an amplifier, we can just solve some equations (either in our computers or with a pencil and paper).

But how do we know that this is the correct equation for this situation. For example, if we choose A as some other value than 1, then the critical value of B also changes.

So help me out here. Please, without resorting to any equations (that may or may not correctly reflect the real world) give me at least a hand waving explanation how having an uncorrected positive thermal coeffiecent WON'T lead to runaway.

In other words, let's use your example of a system with a Beta (your definition) of 1.5, which you claim will be stable. Now let's say that it's a hot day and the ambient temperature goes up 1 degree. But that means that the temperature of the system will actually rise 1.5 degrees. But as soon as it rises 1.5 degrees, then the positive feedback will cause it to rise 1.5 * 1.5 degrees = 2.25 degrees. But as soon as it rises 2.25 degrees, the positive thermal feedback will cause it to rise to 1.5 * 2.25 = 3.375 degrees, and so forth, until the system "latches up" (ie, melts).

What am I missing here?

Do remember that the key thing in the general sense is the product A * Beta. Although for simplicity I have assumed A=1 here, a value of A other than one does not change the impact of the product A * B on the stability. In my earlier post I showed a worked example of where A did not equal 1, and instead was the gain of the output transistor in terms of change in bias current as a function of change in base voltage, taking into account thermal effects.

Sorry, I tried to find that post but couldn't. Perhaps an overzealous moderator split it off into a different thread? Or maybe I'm just too fuzzy from my pain meds.

Do you disagree that the thermal time constant of the heat sink is more than an order of magnitude longer than that of the power transistor die and its package?

It's kind of a separate issue and I don't want to get too sidetracked on this, but I DO at least partially disagree. If the transistor were not bolted to the heatsink, then we would have a problem. But since it IS in relatively intimate thermal contact with the heatsink, then in the real world any potential problems are mitigated to a large extent. The thermal time constant of the transistor die when it is properly mounted to the heatsink is NOT necessarily an order of magnitude different than the time constant of the thermal sensor itself.

It IS true that a BJT can develop "hot spots" where localized thermal runaway can occur. (You may remember the photographs that were published showing this effect on BJT dies when MOSFET's were first introduced, and how the MOSFET's did not suffer from this problem.) If I recall correctly, the formation of these local "hot spots" that could lead to instantaneous thermal runaway is usually referred to by a different name -- "secondary breakdown".

(I'm not an expert on this and could be wrong. Maybe Andy_C will help me out here. He's been kind enough to correct more than one of my misconceptions over the years!)

 

[andy_c]

Actually, I think it should be fairly easy to estimate what the time response is and the time-dependent effects of heat sinking if you know the various thermal resistances (die to case, case to sink, sink to air) and the corresponding heat capacities- it's just a series of three RC time constants. Or am I missing something simple?

Sounds right to me. I'm working on a similar thing as part of a protection circuit that's essentially an analog computer for the instantaneous junction temperature of the output MOSFETs. If one takes the transient thermal impedance plots (thetaJC) from the datasheets and tries to fit them to a single time constant, the fit isn't very good. I noticed in some Fairchild SPICE modeling app notes that they model the FET thermal impedance as a series combination of a number of parallel RCs. So I tried using the Excel solver to do a "best fit" in the time domain of two parallel RCs in series to approximate the junction-to-case thermal impedance, and the results were *much* closer to the datasheet values than the single parallel RC. Maybe there's some kind of separate die-to-substrate and substrate-to-package thing going on.

For the insulators, I'm estimating their surface area, using the thermal conductivity to determine the thermal resistance, and using the mass and specific heat to calculate the thermal capacitance. So I end up with three parallel RCs in series, not including the heat sink. For that I'll just have an LM35 temperature transducer in a TO-220 package on the heat sink.

 

[syn08]

Actually, I think it should be fairly easy to estimate what the time response is and the time-dependent effects of heat sinking if you know the various thermal resistances (die to case, case to sink, sink to air) and the corresponding heat capacities- it's just a series of three RC time constants. Or am I missing something simple?

This approach will lead to an overestimated heatsink, which is ultimately a good thing

Otherwise, determining the exact temperature distribution requires solving the heat equation over the heatsink, device, etc... with some realistic border conditions, which can be done with simulators as good and and precise as Spice. Unfortunately, I'm not aware of any LTSpice equivalent :-(

But I agree that a distributed RC model is good enough for any solid state audio application. The more difficult problem is actually emulating the amp case environment.

 

[Bob Cordell]

I'm trying to hang in there, I really am. But so far you haven't convinced me. There are a couple of problems. The first is that it's not at all clear to me that your equation applies in this instance. Just like SPICE, we are trying to make a mathematical construct that reflects the real world. And then instead of actually having to build an amplifier, we can just solve some equations (either in our computers or with a pencil and paper).

But how do we know that this is the correct equation for this situation. For example, if we choose A as some other value than 1, then the critical value of B also changes.

So help me out here. Please, without resorting to any equations (that may or may not correctly reflect the real world) give me at least a hand waving explanation how having an uncorrected positive thermal coeffiecent WON'T lead to runaway.

In other words, let's use your example of a system with a Beta (your definition) of 1.5, which you claim will be stable. Now let's say that it's a hot day and the ambient temperature goes up 1 degree. But that means that the temperature of the system will actually rise 1.5 degrees. But as soon as it rises 1.5 degrees, then the positive feedback will cause it to rise 1.5 * 1.5 degrees = 2.25 degrees. But as soon as it rises 2.25 degrees, the positive thermal feedback will cause it to rise to 1.5 * 2.25 = 3.375 degrees, and so forth, until the system "latches up" (ie, melts).

What am I missing here?



Sorry, I tried to find that post but couldn't. Perhaps an overzealous moderator split it off into a different thread? Or maybe I'm just too fuzzy from my pain meds.



It's kind of a separate issue and I don't want to get too sidetracked on this, but I DO at least partially disagree. If the transistor were not bolted to the heatsink, then we would have a problem. But since it IS in relatively intimate thermal contact with the heatsink, then in the real world any potential problems are mitigated to a large extent. The thermal time constant of the transistor die when it is properly mounted to the heatsink is NOT necessarily an order of magnitude different than the time constant of the thermal sensor itself.

It IS true that a BJT can develop "hot spots" where localized thermal runaway can occur. (You may remember the photographs that were published showing this effect on BJT dies when MOSFET's were first introduced, and how the MOSFET's did not suffer from this problem.) If I recall correctly, the formation of these local "hot spots" that could lead to instantaneous thermal runaway is usually referred to by a different name -- "secondary breakdown".

(I'm not an expert on this and could be wrong. Maybe Andy_C will help me out here. He's been kind enough to correct more than one of my misconceptions over the years!)

Hi Charles,

Thanks for hanging in there.

Tim's answer above is a good one, but there is also a third way to look at it that also ultimately doesn't depend on much math. This way traces the circuit behavior from the output back to the input. It effectively cuts the feedback loop in doing so. This sometimes makes it easier to analyze. You assume an output change and then trace back to the input to calculate what input change would have been required to generate that output change.

Suppose we have a 100-Watt amplifier with 50V rails, TO-247 output transistors with Theta_cs = 1.3 C/W and 0.22 ohm emitter resistors and biased at 118 mA for a net gm of a transistor and its RE of about 2.3S.

Let’s define the “bias gain” as the change in idle bias current for a given change in power transistor base drive voltage. Without thermal feedback effects, this will simply be the transconductance of 2.3S. We’ll use this as the forward open-loop gain A in the calculation.

For purposes of comparison, let me first show what happens with the approach using the conventional feedback formula.

Looking at it this way, the feedback factor will be B = Theta_JS * Vce * TCvbe

We have, G = A/(1-A*B) = 2.3/(1- 2.3 * 1.3 * 50 * 0.0022 = 2.3/(1-0.33) = 3.43

Notice that the “bias gain” has been enhanced by the factor 3.43/2.3 = 1.5 as a result of the thermal positive feedback.

Notice that A*B is in this equation what I had previously referred to as Beta when I was assuming for convenience A = 1, i.e., Beta = Theta_JS * Vce * TCvce * gm.

Now let’s try the alternative approach by working backwards from the output. Let’s assume a 10 mA rise in idle bias current and work back to the input to see how much base voltage change would have been required to cause this increase.

In the absence of thermal effects, the answer would simply be 10 mA divided by the net transconductance of 2.3S, or about 4.3 mV.

However, when we take into account thermal effects, we recognize that the increase of 10 mA results in a power dissipation increase of 500 mW. This in turn resulted in a die temperature increase of 0.5 * 1.3 = 0.65C. This in turn results in a decrease of Vbe of 1.43 mV. This is 1.43 mV less drive voltage change than we would otherwise have needed in the absence of thermal effects.

So in reality, the change in base voltage needed to cause the 10 mA change in bias current was really only 4.3 – 1.4 = 2.9 mV. As a result the “bias gain” = 10 mA/2.9 mV = 3.4. The enhancement of the bias gain is 3.4/2.3 = 1.5. This is exactly the same answer we got by using the formula.

This is a case where we have modest positive feedback, but with a stable, albeit gain-enhanced, result.

Cheers,
Bob

 

[Bob Cordell]

Oh, I WISH it were that simple. By far the best book on this is a long out-of-print and very hard to find book by Dennis Feucht. He explains it in more detail than anything I found. But everyone basically said the same thing -- add a positive R value to cancel the effective negative R created by the capacitive load.

So I tried crazy values of R, up to a hundred ohms on the outputs and thousands of ohms on the drivers. Barely helped at all, and it totally screwed up everything else about the circuit. I began to see why so many people use an isolation coil...

Hi Charles,

Might a SPICE analysis help in this regard, given that the book is hard to find?

Only half kidding!!

Seriously, I recognize that at minimum a SPICE analysis of this sort of thing (stability of an emitter follower power transistor into a capacitive load) would have to do a good job of including parasitics, especially internal BJT and external parasitic inductances.

Cheers,
Bob

 

[Bob Cordell]

Hi, Mr. Hansen,

This arrangement is used by Mr. Cordell. Imagine the output transistors are Bipolars, not mosfets. R50-R51 are base stoppers (47ohm). Then after these 47ohms, there are C8+R52 and C9+R53 to ground.

Incase of not using output inductor and not using too big base stoppers, is this R+C to ground after 47ohm helps to overcome negative impedance (when bipolar output stage is headed with capacitive load)?

Hmmmm...., now you've got me thinking. Maybe I'll go fire up SPICE .

Cheers,
Bob

 

[PB2]

Re: Re: Re: autobias of mosfets

Hi Pete,

Never mind. As for distortion, I would like to go one step further. The autobias doesn't add any distortion, that is, under steady state conditions. How it behaves under thermal transient conditions in real life, I don't know (as I said before, difficult to measure), but I do know that at 20Hz and skipping the first half cycle, the simulated THD wasn't affected by the bias circuit.

Cheers, Edmond.

PS: To get correct results from a simulation, one needs the BSIM3.3 (or higher) models of the vertical MOSFETs, as lower level models doesn't cover the weak inversion.

Is there a public source for good, BSIM3.3 models?
Always looking for good models, last time I paid for them was
many years ago for IS-SPICE.

Pete B.

 

[Edmond Stuart]

Re: Re: Re: Re: autobias of mosfets

Is there a public source for good, BSIM3.3 models?
Always looking for good models, last time I paid for them was
many years ago for IS-SPICE.

Pete B.

Hi Pete,

As far as I know, the answer is no.
Maybe Andy_C can help you any further.

Cheers,

 

[PB2]

Re: Re: Re: Re: Re: autobias of mosfets

Hi Pete,

As far as I know, the answer is no.
Maybe Andy_C can help you any further.

Cheers,

You remind me, I think Andy posted some output MOSFET models here, I'll search the thread.

Fairchild was mentioned as having BSIM3.3 models, I'll have to take a look on their site.

Does the student version of MicroCap include a good set of models?

Pete B.

 

[Bob Cordell]

I've used PSPICE, where you had to enter a net list in a text file. That sucked. MicroCap has a graphical user interface so you can just draw a schematic. It's a million times better than PSPICE. Plus the post processing was separate in PSPICE. With MicroCap you just push a button and get graphical results.

I downloaded LTSPICE a year or two ago because it was free. I didn't find a single thing about it that was better than MicroCap. While it's not perfect, MicroCap is the best I've used.

MicroCap has a free eval version that is limited to 100 nodes. This is enough to do most audio circuits. The real version cost around $3,000 I think. It may be that LTSPICE doesn't have a circuit-size limitation. That would be the only reason to use it compared to the eval version of MicroCap in my experience.

Hi Charles,

Thanks for getting back to me on this. Ceratinly PSPICE and many of the older versions of SPICE were a royal PIA. I've found LTspice to be very easy to use, especially with a little help from Andy_c in getting over some FFT usage issues.

The fact that it is free and so readily available is very nice, indeed, and I am unaware of any limitation on the number of nodes. I would imagine that it would not be hard to get up to about 100 nodes when simulating an amplifier with about 30 transistors.

Have you ever compared speed of Micro Cap and LTspice? I've heard that for most simulations LTspice is significantly faster than PSPICE or HSPICE. Supposedly, this was in part due to the difficulty of simulating switching power supplies over a large number of cycles, prompting a re-write of some critical routines by the LTspice team to speed it up.

Thanks,
Bob