Xilinx provides an FIR filter compiler on their site, where Vivado appears to generate the desired code. You can find detailed explanations here:
https://docs.xilinx.com/r/en-US/pg149-fir-compiler/Coefficient-Padding?tocId=8Msr0aIMrXPOYpxOCiIYjQ
However, just as software compilers might not always optimize for minimal code output, the same holds true for FPGAs. The likelihood of pre-existing compilers generating code that fits within xc6slx9 is low.
I personally combine individual memories and multipliers, probably a strategy also used by olo111. This guy has published a code for double oversampling, which could be insightful. The coefficients appear to be 16 bits:
https://audio-diy.hatenablog.com/entry/FIR_x2_howtouse
Primarily, memory is used as a ring buffer, facilitating multiplication with the filter coefficients. During oversampling, the calculations for inserted zeros become unnecessary, reducing computational load. However, the output frequency increases, which means the computation time remains constant.
For a standard FIR filter, the principle remains similar.
It can be implemented using four multipliers, a few memories, and adders. It would not always be necessary to deliberately employ a half-band filter. Individual code implementations might slightly differ based on input and output frequencies, but the underlying principle remains the same.
https://docs.xilinx.com/r/en-US/pg149-fir-compiler/Coefficient-Padding?tocId=8Msr0aIMrXPOYpxOCiIYjQ
However, just as software compilers might not always optimize for minimal code output, the same holds true for FPGAs. The likelihood of pre-existing compilers generating code that fits within xc6slx9 is low.
I personally combine individual memories and multipliers, probably a strategy also used by olo111. This guy has published a code for double oversampling, which could be insightful. The coefficients appear to be 16 bits:
https://audio-diy.hatenablog.com/entry/FIR_x2_howtouse
Primarily, memory is used as a ring buffer, facilitating multiplication with the filter coefficients. During oversampling, the calculations for inserted zeros become unnecessary, reducing computational load. However, the output frequency increases, which means the computation time remains constant.
For a standard FIR filter, the principle remains similar.
In order to doubling LRCK and BCK ,I couldn't understand the code Inside of https://github.com/AUDIY/FIR_x2/blob/main/04_FIR_COEF/FIR_COEF.v as follow:
always @ (posedge MCLK_I) begin
LRCKx2_p1 <= LRCKx_O;
LRCKx2_p2 <= LRCKx2_p1;
/* Add BCKx_O Output Register, 2023/09/03 */
BCKx2_p1 <= (ADDR_WIDTH >= 8) ? BCKx_O : 1'b0; // Change BCKx2 Generation (2023/11/26)
BCKx2_p2 <= BCKx2_p1;
end
this code just make LRCK and BCK delay two cycle of MCK_I ?
always @ (posedge MCLK_I) begin
LRCKx2_p1 <= LRCKx_O;
LRCKx2_p2 <= LRCKx2_p1;
/* Add BCKx_O Output Register, 2023/09/03 */
BCKx2_p1 <= (ADDR_WIDTH >= 8) ? BCKx_O : 1'b0; // Change BCKx2 Generation (2023/11/26)
BCKx2_p2 <= BCKx2_p1;
end
this code just make LRCK and BCK delay two cycle of MCK_I ?
I posted some information and measurements related to pcm2dsd in RTZ dac thread.
Hello, got the module PCMtoDSD assembled long ago. Now, while friend Felipe kindly is updating the firmware for me, I look for parts to implement it in my stereo.
I am using television as only digital source, Hdmi arc cable should provide good I2s after Ian Canada Hdmi receiver, that I am willing to connect to PCMtoDSD.
But after reading the thread, learned this modulator must be ideally handled by same 22,xxx/ 24.xxx frequency clocks used in the development.
But no idea what value is in the internal clock frequency on the TV.
That could be a concern?
Also in order to improve musical performance, I decided buy a fifo reclock. I like Ian Canada McFIFO/McDualXO.
Should I place it after the PCMtoDSD as stated here for correct noise clean up?
DAC is passive 4rth order high pass filter "NoDac".
Jordi
I am using television as only digital source, Hdmi arc cable should provide good I2s after Ian Canada Hdmi receiver, that I am willing to connect to PCMtoDSD.
But after reading the thread, learned this modulator must be ideally handled by same 22,xxx/ 24.xxx frequency clocks used in the development.
But no idea what value is in the internal clock frequency on the TV.
That could be a concern?
Also in order to improve musical performance, I decided buy a fifo reclock. I like Ian Canada McFIFO/McDualXO.
Should I place it after the PCMtoDSD as stated here for correct noise clean up?
DAC is passive 4rth order high pass filter "NoDac".
Jordi
@roderickvd thanks, you guessed right, is my bad. I notice now that Hdmi Arc despite as a new interface for audio, not handles beautiful I2s signal. Only SPDIF stream tight on pin 14 (HEAC), so I will continue using my dedicated good quality optical toslink cable and buy a receiverPi module to get I2s from that.
I stated before, as "clock to resample the signal" this extra only one clock that Marckw4 mentioned as as TV direct stream solution.
Limited english my apologies.
I know PCM2DSD needs 22M/24M, but not sure wheter to place, before or after it.
If before, then is in need for further clock cleansing thereafter? in all scenarios?
Limited english my apologies.
I know PCM2DSD needs 22M/24M, but not sure wheter to place, before or after it.
If before, then is in need for further clock cleansing thereafter? in all scenarios?