Hi, All!
Hi, @olo111, @PJotr25 and @Markw4 - your work is incredible!
I want to ask you (if it not difficult for you) to synthese the bitstream (V3) to GOWIN Tang Nano 9k (or 20K, if you can).
This boards are very cheap and useful for audio aims.
GOWIN IDE is free and "eat" verilog very well ))
Thank you!
Hi, @olo111, @PJotr25 and @Markw4 - your work is incredible!
I want to ask you (if it not difficult for you) to synthese the bitstream (V3) to GOWIN Tang Nano 9k (or 20K, if you can).
This boards are very cheap and useful for audio aims.
GOWIN IDE is free and "eat" verilog very well ))
Thank you!
Why do you say the existing work is incredible? Why should it be ported to something else, what's wrong with it now?
I don't know of any services that would do these, apart from perhaps JLCpcb, however I have a couple of these pcbs spare and at least some of the required components, having built 2 already. I can probably manage a 3rd before my eyes give up completely, if you can source the remaining components. Provided you're not in any huge rush, what with Christmas coming up and all.
Do you have the stencil for this board?
For JLC to provide assembled boards I imagine you would need to provide pick and place data from the PCB design package, plus there willl be a minimum order qty.
cound I get PCM2DSD HDL source?It's nice to present this project - separate delta sigma modulator for a dsc2 dac.
Special thanks to Jussi and Pavel.
The basic idea is to convert pcm to a dsd stream without the use of a PC.
Design flow goes as follows:
i2s serial data is converted to parallel, next we have the first interpolation fir filter,
in this filter the data is oversampled x2, x4 or x8 - this depends on the incoming data rate.
(for 44.1kHz we have x8 interpolation, for 96kHz x4 and for 192kHz x2)
next, the data is going to the two stage CIC filter and is oversampled x32 to final x256
Then the data is going into the sigma delta 7 order modulator, which has classical CRFB structure,
as I said earlier all arithmetics are done in CSD arith, so no multipliers here.
all coefficients are carefully optimized using delsig package
If someone asks, yes, there are g0, g1, g2 coeffs.
At the end the dsd streams are time aligned using ODDR2 primitives
XC6SLX9 is almost full, so there is no ability to add anything
The device was designed to run with a mclk of 22/24 MHz.
To upload the attached bitstream file to the board you need a Xilinx programmer cable and Xilinx program Impact.
In the next post my friend PJotr will post gerber files, BOM and some measurements.
I hope this project will be interesting for someone.
DIY use only!
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Update 24.07.2023 New firmware !
First of all, I'd like to thank Markw4 for your help!
The entire software is practically completely new.
The first FIR filter now has x8 fixed interpolation (fs 44.1kHz - 192kHz), has 2048 taps, 32 bit coefficients and 100dB stopband attenuation.
Then it's a two-stage CIC filter and it's oversampled to the final x256. Oversampling depends on the rate of incoming data.
Then we have a 5-order sigma delta modulator, which has classical CRFB structure, with noise shaping and dithering.
And as before, at the end the dsd streams are time aligned using ODDR2 primitives.
We made tens of different firmware configurations and finally chose this version after listening sessions.
Latest firmware:
https://www.diyaudio.com/community/threads/simple-dsd-modulator-for-dsc2.370177/page-42#post-7407495
do interpolation fir and CIC use xilinx IP core?Exciting project. Could you clarify CSD arithmetic in detail or reference paper? I can understand what you mean; xc6slx9 is at max capacity. Two x256 upsampling FIRs occupy almost everything. It's beyond my imagination why the rest can calculate two 7th order DSM with three local FBs(g0,g1, and g2) though I think two is enough for 7th order, IMO. The only answer is probably CSD.
In this project, we are using small-scale FPGAs like the xc6slx9 (which is QFP and hand-solderable). Utilizing existing IP would likely exceed the capacity. Therefore, I use individual multipliers and adders, employing ingenuity similar to programming within the limitations of older 64-kilobyte memories to fit within the capacity. Even in CSD, I'm sure craftsman skills are utilized to reduce the number of cells. The same applies when executing regular DSM operations. I believe the limit for xc6slx9 would be around 6th order with a 256OSR.