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Reference DAC Module - Discrete R-2R Sign Magnitude 24 bit 384 KHz

There seems to be a coupling between how much money or resources you you spend on something and how much improvement you want to hear, the key is doing ABX listening test.... As an engineer I like to design for cost, choosing lowest cost parts that fit the need, without over designing. It would be easy (and stupid) to just choose the best and most expensive parts....

Indeed there is a solid relation between cost and quality even if sometimes the selling prices become greedy.

MSB clocks are the perfect example: you cannot build a very low noise oscillator at Crystek price level (or Silabs), only the crystal costs more.
The selling price is exagerate, but if you build yourself a low noise oscillators expect a cost of several hundreds USD and not 25 USD like the Crystek, it's impossible.

The same for the MSB DAC system, 100000 USD or so is a bit high, but to build yourself a comparable system you have to spend several thousands of USD, not 300 Euro.

I think that designing for cost is more a commercial than an engineering choice.
If you take away the commercial aspect you can design for the best as possible regardless of the cost.
It's a different approach, maybe more diy oriented.

IMHO it's not that simple to choose the most expensive parts and make the best devices.
To design our oscillators we have chosen the best parts but to achieve SOTA performance we have spent several years and several iterations (design, layout, measurements, tuning and so on).
 
MSB clocks are really Galactic, they have very low phase noise, in the region of the best oscillator on the market like Wenzel and Oscilloquartz (and my new oscillators).
Then one can argue if 19000 USD is the right price.

Andrea, do you know if the MSB Galactic clock have variable frequency ? I believe they have the same kind of Digital PLL like me, at least they used to use a Si570, just like what Rockna do....
 
I don't believe, they use a pair of oscillators at 22.5792 and 24.576 MHz so the PLL would not make sense, a programmable divider is more than enough.
And it would not make sense to spoil such fine oscillators with a PLL that adds huge phase noise.

Maybe they use the Si570 in the entry level DAC but not in the top devices.
 
By the way, the Si570 is no longer the top of the line model of SI Labs. Perhaps, Soeren, you could consider to switch to the new ones for the upcoming DAMs.

I have of course looked at the new parts, but they're not really that much better than the si570....

It's not a good idea, Silabs makes oscillators for telecommunication, not for digital audio.

Applications from the datasheet:
SONET/SDH/OTN
Gigabit Ethernet
Fibre Channel/SAS/SATA
PCI Express
3G-SDI/HD-SDI/SDI
Telecom
Switches/routers
FPGA/ASIC clock generation

I don't need a part to be marketed for "Digital Audio" for me to use them....
 

TNT

Member
Joined 2003
Paid Member
So the proof of the pudding is: can we hear it?

In the left corner with red trunks - Sören - who punches "adequate - better can't be heard..."

and in the right corner - with green trunks - Andrea - jabbing "every little reduced (close in) phase noise dB turns into improvements"

Over 10 rounds or KO... readyyyy to rumble...

Who are the judges?

//
 
Hi Soren,
where did you see that? it is very doubtful that such low-quality clocks can be from such companies

The Si570 is, despite what other people say, actually a very high performance part.

Look at the drawings of their clock on Rockna's website:
Wavedream DAC | Rockna Audio
And compare with the drawing in the si570 datasheet.
And look at this picture, U4 next to the Spartan-6 FPGA:
https://headmania.files.wordpress.com/2014/04/rockna-wavedream-review-2.jpg
 

TNT

Member
Joined 2003
Paid Member
Rockna...

"The conversion clock is controlled with 1 ppb precision, while exhibiting about 300 fS of jitter. The smallest jitter figure in the world? No. The smallest jitter figure where actually matters? Probably."

Probably - LOL!

Company legal at work....

//
 
The Digikey price for one is only about 2$more expensive. At least for marketing reasons this should be worth the money ... you can boast with half the jitter than before ;-)

As Andrea would say, look at the phase noise....

And I like to keep down on different parts, I already use four different Si514/Si570 types, and I try to avoid the need for updating firmware....
 
So the proof of the pudding is: can we hear it?

In the left corner with red trunks - Sören - who punches "adequate - better can't be heard..."

and in the right corner - with green trunks - Andrea - jabbing "every little reduced (close in) phase noise dB turns into improvements"

Over 10 rounds or KO... readyyyy to rumble...

Who are the judges?

//

I think everyone could do the test althoug is not very simple and finally the board is gone.

To do the comparison you need the original board and another one to heavily tweak: you could feed the LVC595s with Ian's stuff (FIFO buffer and I2S to PCM boards) and a low noise oscillator.
I don't know if it's possible until I get the board, maybe you need to cut some traces.
 

TNT

Member
Joined 2003
Paid Member
Maybe its better to take a completely PN optimised platform - like your upcoming DAC - and compare 2 versions of them,; one with your oscs and one with a poorer osc (maybe a Si). Given that your DAC really sounds equally or better than the DAM in general :) Who is to judge - an in what system? It is so bleeding hard to make fair, objective comparisons.

Given your DAC is OK, is probably a better evaluation platform for judging if PN really matters. Then comes the testig setup... DBT? or ....??

It aint easy either way :)

PS: Add to that that different DAC architectures are more or less sensitive to jitter/PN.

//
 
Last edited:
Rockna...

"The conversion clock is controlled with 1 ppb precision, while exhibiting about 300 fS of jitter. The smallest jitter figure in the world? No. The smallest jitter figure where actually matters? Probably."

Probably - LOL!

Company legal at work....

//

Well, it depends on the integration bandwidth of the measured jitter, maybe 300Hz-3KHz the standard for telecommunications.

Soren,
is it possible to feed the 595s from external signals excluding the whole front-end?
 
So the proof of the pudding is: can we hear it?


//


Years ago i tested the 570 in Ian's fifo against the Crysteks. No comparison, even though the 570 had a lower noise regulator next to it. I don't think my conclusion was system or taste specific, the 570 brought the sigma delta dac down in every audible respect.

Otoh, the same part seems to perform well in the 1941, so R2-R dacs may indeed not be so sensitive to clocks.

Since day 1 of the DAM i have been wishing for a minimalist board from Soekris. One with no fifo, no onboard filters, no onboard regulation apart for the micro and fpga and capable of accepting and selecting external clocks. And reclocking after the fpga with a potato flip flop. Apparently Søren thinks there is no market for such a device and he may be right. Doesn't stop me from wishing :)