AJC,
the math is simple, this dac is 24 bit resolution and 13-14 bit precision.
The sign magnitude notation, since MSB bits switch only when needed, should theoretically give lower glitch and better THD, but the precision doesn't change.
Using 0.001% resistors tolerance you can reach 16-17 bit precision.
I meant a single ladder per channel (like PCM1704), while this dac use dual ladder per channel, that's halves the precision, since the resistors tolerance affects separately upper and lower portion of the wave.
Andrea
I'm sorry for the low prices. Maybe I should start using buzz words like "Platinum", "Signature", "Femto Clock", "Carefully tested", "Select component", "Exclusive Technologies".... And then add $100 per word used
ahahaha, you understood the second degree french humour very well, I haven't any problem of translation... you price is honnest for the quality of the project, so thank you for that
yes you should add these words for the V2 at 100 euros each but without sending the improved V2 boards or second sending batch after! Notice as showed you can't use "Total" as it's copy righted at 9000 euros the standalone word !Off course you need to send the V1 first batch at the friendly price you gave us ( oups, am i on the V1 list
!)signé : Papa Madov !
Sorry, have to leave, there are two people in the street fighting each other because talking about your DAC and because thet can't wait anymore as well!
..... have a people from Poland ringing at the bell of my door with a Nobel price near him !
PS :
(This second degree moment is offered by Geekey, TNT & Eldam to allow you to wait the DAC
)cheers all
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Thanks for the reply, but you are still confusing me. I think we can agree that the PCM1704 is also a sign-magnitude design and uses one ladder for each half of the waveform.
And counting the resistors in Soren's photo, I see just 2 ladders per channel, one each for +/-. Am I not counting correctly?
(BTW, he goes to 28 bits to have resolution for volume control--should still be 16-bit at -72dB.)
As an aside, when BB introduced PCM63, they referred to what from my reading is the same ladder structure as PCM1704, but called it Colinear. Then with PCM1704 they refer to it as Sign-Magnitude.
Are they not the same structure? Am I missing something?
Regards,
Alex
That is an interesting subject indeed.
I have several questions for Søren:
- How can the user set the digital filter parameters, including anti aliasing filters?
- How many taps do we have per channel?
- How do you deal with the different sampling frequencies the DAC will automatically adapt to (or did I understand it wrong?), as it will change the behavior of the FIR filters?
Alex,
both PCM63 and PCM1704 are Collinear DAC, or sign magnitude, that's the same thing.
But they use a single ladder per channel, not a single ladder for each half of the waveform. See post #347.
Finally, BB DACs use 2 ladders in total, while Soekris DAC use 4 ladders in total, that decreases the precision.
Andrea
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Since we all agree that this is Søren's DAC and is not for customization (if you want to, you can order the board and customize it yourself)... I'd vote for the discussion on the design merits to go elsewhere [why discuss things that won't change right now???].
If you can't accept that Søren's design considerations allow for 14-bit precision resistors to provide for 24-bit resolution, please feel free to use other chips. Last I read, I don't believe Søren is forcing anyone to buy this...
I agree with roger... please let's discuss about the filters and how to implement useful ones. Because I'm such a noob, would also like more information on how to handle control via the serial port - hopefully it's possible to use Arduino for this?
Cheers,
If you can't accept that Søren's design considerations allow for 14-bit precision resistors to provide for 24-bit resolution, please feel free to use other chips. Last I read, I don't believe Søren is forcing anyone to buy this...
I agree with roger... please let's discuss about the filters and how to implement useful ones. Because I'm such a noob, would also like more information on how to handle control via the serial port - hopefully it's possible to use Arduino for this?
Cheers,
I expect so...
This DAC could very well be the start of some additional product development
Thank you Andrea. I forgot that this was all discussed months ago in this thread. I reread all the posts around that, including looking at the diagrams. I see that even you were/are puzzled about how BB accomplished sharing a single ladder for +/- of waveform--and that their own spec sheets don't tell (the block diagram in PCM1704 datasheet showing separate A and B DACs is what had me arguing with you in the first place).
So maybe it is not fair to criticize Soren for no implementing a single shared ladder when nobody here knows how BB accomplished that. And I don't think it takes too much away from the benefit of his providing us with a sign-magnitude R2R.
What else on earth like this is available at this price (a stereo pair of PCM1704 is now $150 by themselves)?
Lastly, setting aside price, are you aware of any discrete R2R DAC units being sold that do use a single shared ladder? MSB Tech is the only one I know where we can't see the inside of their modules to count resistors...
Anyway, thanks again.
P.S. OT: Are you offering your hand built clock modules for sale? I'd be interested in a pair 22.xxxx and 24.xxxxMhz for a different project.
hmmm.
My understanding is that one needs 4 pieces of 1704 to make a balanced DAC, so, what, $300.00 right there just for chips.
MSB modules are enclosed, so who knows for sure what is in there. I asked an MSB engineer once at RMAF, all he would say is discrete resistors, not what ones, or any mention of precision values... I suspect some variation on Texas Components z foils, but who knows for sure... One thing is for sure, MSB Platinum level DACs measure to better than 19 bits of resolution (in Stereophile measurements)...
In any case, MSB also uses four of their modules for any of their balanced DACs. Single ended DACs from them like their more affordable (relatively) "Analog DAC" use two modules, and the more expensive models use four modules-so I would guess a single ladder in each module...right?
My understanding is that one needs 4 pieces of 1704 to make a balanced DAC, so, what, $300.00 right there just for chips.
MSB modules are enclosed, so who knows for sure what is in there. I asked an MSB engineer once at RMAF, all he would say is discrete resistors, not what ones, or any mention of precision values... I suspect some variation on Texas Components z foils, but who knows for sure... One thing is for sure, MSB Platinum level DACs measure to better than 19 bits of resolution (in Stereophile measurements)...
In any case, MSB also uses four of their modules for any of their balanced DACs. Single ended DACs from them like their more affordable (relatively) "Analog DAC" use two modules, and the more expensive models use four modules-so I would guess a single ladder in each module...right?
I'm not criticizing Soren, just for debate around a project published in a diy forum.
My personal choices would follow a different way. Above all, I like to think to a "system" rather than a dac, as I said previously.
But my free time is very little, so I have no chance to start similar project.
I believe Soren has the ability to design a system, since he is familiar with FPGA and uC. I hope he will start such kind of project in the future.
About my clock board, this is the link:
http://www.diyaudio.com/forums/digi...phase-noise-jitter-crystal-oscillator-19.html
I offer PCBs and crystal at cost, as I said I have no commercial interest.
I'm going to close the list next days.
Hi Barrows:
Good to "see" you. Yeah, 1704s are getting really pricey. T.I. ruins only one batch year. Still, the comparison should be to just 2 pieces, not 4 as Soren's DAC does not have a full balanced output (though I guess his output drivers--which will bypass--are balanced). The board is a bargain nonetheless.
Dustin (MSB's engr.) once told me that they pay to have their ladder networks laser trimmed by an outside firm. I think he even flashed us a billing sheet for the different levels of module (Gold, Platinum, Diamond, etc.) and indeed their own costs were high. (This was over 10 years ago when we at Hovland were entertaining the possibility of OEMing their modules; the prices scared us off!)
But back to the point: I don't know that MSB's R2R ladder modules are even configured as sign-magnitude style, so the question of if they matrix one ladder to serve both plus and minus--but still with the sign-magnitude scheme may not even be relevant.
Plus it is doubtful they are doing so; it would seem to require some offset/delay and switching to accomplish. See the September discussion of this here:
http://www.diyaudio.com/forums/vend...-magnitude-24-bit-384-khz-35.html#post4045178
Still confusing and somewhat inconclusive--at least about HOW Burr Brown did it. Maybe someone will exhibit the die film of a PCM63 or PCM1704!
I do wish Soren would update us on when first production is coming and maybe send out an e-mail so we can know if we are in the first batch or second batch.
I don't want to re-launch "the clock war" - but I found a very on topic application note from Silicon Labs about RMS jitter using Silabs clock (51x, 570, ...) with various FPGA (and of course Xilinx Spartan 6).
It lacks graphics showing jitter in the audio range, but I guess it can still be of interest.
http://www.silabs.com/support documents/technicaldocs/AN699.pdf#p=2
Results of " Silicon Labs Phase Jitter Performance vs. Xilinx Phase Jitter Requirements "
Ref Clock 100Mhz: 2.22 ps RMS
SI 51x (used in this dac): 1.1 ps RMS
SI 53x/57x : 0.23 ps RMS
It lacks graphics showing jitter in the audio range, but I guess it can still be of interest.
http://www.silabs.com/support documents/technicaldocs/AN699.pdf#p=2
Results of " Silicon Labs Phase Jitter Performance vs. Xilinx Phase Jitter Requirements "
Ref Clock 100Mhz: 2.22 ps RMS
SI 51x (used in this dac): 1.1 ps RMS
SI 53x/57x : 0.23 ps RMS
SiLabs AN699 is not really relevant here, it's about jitter specifications when using the FPGA's Serdes transceivers and/or PLL's.
In the R-2R DAC the clock from the oscillator goes into the FPGA's using LVDS balanced signaling, into the main low skew low jitter clock distribution network in the FPGA, then to a flip-flop embedded in the output cell and then out to the LVS595 registers.
Can't really be done better. It's waste of time talking about lower jitter if not using balanced LVDS signals, as a single ended CMOS signal has rise/fall times of in 0.5-2 nS range. Which when feed into a normal DAC chip will make talks about 1 pS jitter a joke, think about the noise in the input buffer's power supply....
Instead of oscillator jitter you should rather talk about signal quality, transmissions lines and terminations, I believe the difference in what you hear comes from other factors then the oscillators themselves....
In the R-2R DAC the clock from the oscillator goes into the FPGA's using LVDS balanced signaling, into the main low skew low jitter clock distribution network in the FPGA, then to a flip-flop embedded in the output cell and then out to the LVS595 registers.
Can't really be done better. It's waste of time talking about lower jitter if not using balanced LVDS signals, as a single ended CMOS signal has rise/fall times of in 0.5-2 nS range. Which when feed into a normal DAC chip will make talks about 1 pS jitter a joke, think about the noise in the input buffer's power supply....
Instead of oscillator jitter you should rather talk about signal quality, transmissions lines and terminations, I believe the difference in what you hear comes from other factors then the oscillators themselves....
Dear Søren:
I think it has been a while since you gave us an update on the status of production. Can you please do so?
Also, it would be extremely helpful you could:
a) Tell us how many boards will be done in the first batch--and when;
b) Tell us how many and when you think the second batch will be;
And most importantly
c) Begin sending out e-mails to everyone who has requested a board and give us each some indication of if we can expect to have delivery from the first or second batch (I realize that will change for some near the dividing line if some early people cancel their reservation.)
Some (many?) of us are anxious to plan our projects around your R-2R board, and having some idea of where we stand in your queue would be VERY helpful.
Thanks and regards,
Alex
I think it has been a while since you gave us an update on the status of production. Can you please do so?
Also, it would be extremely helpful you could:
a) Tell us how many boards will be done in the first batch--and when;
b) Tell us how many and when you think the second batch will be;
And most importantly
c) Begin sending out e-mails to everyone who has requested a board and give us each some indication of if we can expect to have delivery from the first or second batch (I realize that will change for some near the dividing line if some early people cancel their reservation.)
Some (many?) of us are anxious to plan our projects around your R-2R board, and having some idea of where we stand in your queue would be VERY helpful.
Thanks and regards,
Alex
"Quoted" from the Xilinx forum link:
Jitter - Xilinx User Community Forums
The System jitter are the jitter on the clock signals themselves, and then the flip-flop itself will add even more..
Another issue are the input and output "hardware" (also including the LVDS standard) as it is impossible for the flip-flop to drive or source signals directly from the IO pad…
Up to 1 ns jitter may be added by the IOB driver / receiver…
However a Spartan-6 based DAC should perform similarly to any modern DAC chips so why worry..
The PCB traces from the FPGA to the LVS595 registers, the LVS595 performance, the PCB traces connecting up the R2R ladder, and the PSUs that are the reference for the conversion are what will have precedence for the SQ.
There are DACs among the best reputed DACs selling for 10s of thousands of $ using FPGAs and CPLDs.
And some of them uses CPLDs with much much lesser specs and performance than a Spartan-6, and no re-clocking -> CPLD connected directly to PCM1704 or discrete R2R...