Edmond Stuart said:
Hi Edmond,
I was asking if you would post the simulation of TMC applied to my circuit, where you indicated that the results were not as good as you expected.
I'm most interested in the schematic, but if it is available in an LTSPICE form where I can directly duplicate the simulation, that is even better.
Thanks,
Bob
Bob Cordell said:
Hi Bob,
First, my apologies for confusing you with Glen.
For the simulation I've used exactly your schematic, except for one additional cap (C12) and one resistor (R62), see picture below. Regrettably I've only a Micro-Cap version of the schematic.
Regarding the performance, THD20 dropped from 6ppm to about 2.5ppm. Decreasing R62 any further doesn't doesn't improve this figure. Actually, the "diminishing of returns" starts already at 3kOhm.
Cheers, Edmond.
Attachments
Edmond Stuart said:
Hi Edmond,
Thanks for this information. Its actually pretty impressive that the O'l Gal got down to 2.5 ppm with TMC.
Actually, what I think you are seeing is that you've reached the limit imposed by that implemenation of the input stage/VAS. That may be why you are not seeing a bigger relative improvement with the application of TMC. Unless measures are taken to mitigate Early effect and input stage common mode distortion, I don't think it can go much lower even with a perfect output stage.
In order to evaluate the effectiveness of TMC, I simulated it without EC, so I would not bump up agaist limits imposed by the input stage and VAS.
The circuit is shown below. It uses a single V MOSFET output pair driving 8 ohms and biased at the usual 150 mA. I did include those nice VAS driver transistors you use, and I also put in some mitigation of input common mode effects in the form of a driven cascode above the input transistors. Note that I like to tap off the TMC from the first buffer after the VAS. This circuit has the same 2 MHz gain crossover as the original MOSFET amplifier that employed error correction.
Without TMC, THD-20 was 0.0083%. With TMC, it droppoed to 0.001% - almost in the range of the design that used EC! Bottom line is that TMC applied to my input VAS architecture in this case gave an 8.3:1 reduction in distortion, or about 18 dB. So I think it is safe to conclude that TMC is quite effective with my input/VAS architecture.
Since I usually get a 30 dB improvement with EC, it is tempting to speculate how low it might go with EC added if the input stage/VAS is revised to include Early Effect mitigation. In an ideal world, the effects of TMC and EC would add, but that may not always be the case.
Cheers,
Bob
Attachments
Edmond Stuart said:
Hi Glen,
I'm sorry, I didn't spiced your amp yet due to lack of time and a flu. However, I've successfully spiced another bipolar amp (D. Self's blameless amp) with TMC (5 years ago!).
I know, these ON Semi (=Modpex) models are notorious bad. Regrettably I don't have better MJE15028 models.
BTW, I did a quick sim of Bob's amp with TMC, but the improvement was rather disappointing. For some reason his front end is apparently less suitable for TMC.
Cheers, Edmond.
Thanks Edmond.
Though the MJE15028/29 models seem to be bunk, I’m getting reasonable results from the On Semi MJE15032/33 models.
However these are the only workable driver trannie models suitable for high power BJT output stages I’ve got, which is a little restrictive
Those fancy Toshiba and Sanyo trannies are nice, but not suitable for power BJT drivers; only suitable for use as MOSFET drivers and pre-drivers on BJT output stages. Anyway, I’ve finalised the design of my amp now. It is simulating just under 4ppm THD-20 delivering 300W into 4 ohms with exaggerated inductances in the tracks of the output devices and parallel pairs of driver trannies and a 1MHz unity gain cross over. The TMC transition is set to what I think is a conservatively low frequency too, so I’ll see how she goes.
Still using class A, but no EC. The 800W of class A heat doesn’t do very much to reduce the 300W THD (over D-self optimal class B), believe it or not (at these class A power levels driving the massive number of trannies required to get rid of the heat introduces problems of it's own), but the low power THD is an entirely different story
Also, Rachel isn't replying to any of my emails, so I will need my amplifier to keep me warm instead
Cheers,
Glen
Cmcl
Hi abzug,
I've put here a simplified diagram of a common mode control loop (CMCL), stripped of all bells and whistles.
The purpose of this arrangement is to maximize the gain and at the same time to keep the quiescent current of the VAS under tight control.
There are three main components:
1. A CFB input stage, Q4, Q5, Q8 and Q9
2. The CMCL stage, Q7, Q10, Q11 and Q12
3. The top and bottom VAS, Q13, Q15, respectively Q14, Q18.
It is clear that without some measures, the input stage will turn both VASses hard on and an unacceptable high common mode current will arise. In principle, one can avoid this by shunting each VAS input with a resistor (a few kOhm), However, this will spoil the gain considerably. In my opinion, a bad idea, the more so as this loss of gain has to be compensated by an additional gain stage somewhere else in the signal path.
By means of feedback of the VAS common mode current, however, we can leave the gain unaffected.
This is done by sensing both VAS currents, add them together (Q11, Q12) and subtract the result via current mirrors (Q7,Q10) from the standing current of the input stage (at the collectors of Q8,Q9)
In the original PGP amp, separate transistors were used for sensing the VAS current. In this (low cost) version however, the collectors of the "beta enhancement trannies" (Q13, Q14), which would otherwise be tied to ground, are used for this purpose.
Ic(Q13) =~ ( Ic(Q15) * R29 + Vbe(Q15) ) / R21
Also notice that this version makes use of very simple current mirrors (Q7, R9, R18, respectively Q10,R12,R20), instead of the more commonly used two transistor topology. One might think that this arrangement is too strongly temperature dependent. That's not the case, as the positive tempco of the current mirrors
Iout =~ ( Iin * R18 - Vbe(Q7) ) / R9
roughly equals the negative tempco of the sensing stage, see above equation.
I hope this explanation is sufficient.
BTW, A CMCL also solves the "fighting VAS" issue, see:
http://www.diyaudio.com/forums/showthread.php?postid=1338861#post1338861
Cheers, Edmond.
abzug said:Hard not to... I'm having trouble following itCan you give a quick explanation or a reference?
Hi abzug,
I've put here a simplified diagram of a common mode control loop (CMCL), stripped of all bells and whistles.
The purpose of this arrangement is to maximize the gain and at the same time to keep the quiescent current of the VAS under tight control.
There are three main components:
1. A CFB input stage, Q4, Q5, Q8 and Q9
2. The CMCL stage, Q7, Q10, Q11 and Q12
3. The top and bottom VAS, Q13, Q15, respectively Q14, Q18.
It is clear that without some measures, the input stage will turn both VASses hard on and an unacceptable high common mode current will arise. In principle, one can avoid this by shunting each VAS input with a resistor (a few kOhm), However, this will spoil the gain considerably. In my opinion, a bad idea, the more so as this loss of gain has to be compensated by an additional gain stage somewhere else in the signal path.
By means of feedback of the VAS common mode current, however, we can leave the gain unaffected.
This is done by sensing both VAS currents, add them together (Q11, Q12) and subtract the result via current mirrors (Q7,Q10) from the standing current of the input stage (at the collectors of Q8,Q9)
In the original PGP amp, separate transistors were used for sensing the VAS current. In this (low cost) version however, the collectors of the "beta enhancement trannies" (Q13, Q14), which would otherwise be tied to ground, are used for this purpose.
Ic(Q13) =~ ( Ic(Q15) * R29 + Vbe(Q15) ) / R21
Also notice that this version makes use of very simple current mirrors (Q7, R9, R18, respectively Q10,R12,R20), instead of the more commonly used two transistor topology. One might think that this arrangement is too strongly temperature dependent. That's not the case, as the positive tempco of the current mirrors
Iout =~ ( Iin * R18 - Vbe(Q7) ) / R9
roughly equals the negative tempco of the sensing stage, see above equation.
I hope this explanation is sufficient.
BTW, A CMCL also solves the "fighting VAS" issue, see:
http://www.diyaudio.com/forums/showthread.php?postid=1338861#post1338861
Cheers, Edmond.
Attachments
Re: Cmcl
This is a nice circuit and a nice explanation, Edmond.
Bob
Edmond Stuart said:
Hi abzug,
I've put here a simplified diagram of a common mode control loop (CMCL), stripped of all bells and whistles.
The purpose of this arrangement is to maximize the gain and at the same time to keep the quiescent current of the VAS under tight control.
There are three main components:
1. A CFB input stage, Q4, Q5, Q8 and Q9
2. The CMCL stage, Q7, Q10, Q11 and Q12
3. The top and bottom VAS, Q13, Q15, respectively Q14, Q18.
It is clear that without some measures, the input stage will turn both VASses hard on and an unacceptable high common mode current will arise. In principle, one can avoid this by shunting each VAS input with a resistor (a few kOhm), However, this will spoil the gain considerably. In my opinion, a bad idea, the more so as this loss of gain has to be compensated by an additional gain stage somewhere else in the signal path.
By means of feedback of the VAS common mode current, however, we can leave the gain unaffected.
This is done by sensing both VAS currents, add them together (Q11, Q12) and subtract the result via current mirrors (Q7,Q10) from the standing current of the input stage (at the collectors of Q8,Q9)
In the original PGP amp, separate transistors were used for sensing the VAS current. In this (low cost) version however, the collectors of the "beta enhancement trannies" (Q13, Q14), which would otherwise be tied to ground, are used for this purpose.
Ic(Q13) =~ ( Ic(Q15) * R29 + Vbe(Q15) ) / R21
Also notice that this version makes use of very simple current mirrors (Q7, R9, R18, respectively Q10,R12,R20), instead of the more commonly used two transistor topology. One might think that this arrangement is too strongly temperature dependent. That's not the case, as the positive tempco of the current mirrors
Iout =~ ( Iin * R18 - Vbe(Q7) ) / R9
roughly equals the negative tempco of the sensing stage, see above equation.
I hope this explanation is sufficient.
BTW, A CMCL also solves the "fighting VAS" issue, see:
http://www.diyaudio.com/forums/showthread.php?postid=1338861#post1338861
Cheers, Edmond.
This is a nice circuit and a nice explanation, Edmond.
Bob
Re: Cmcl
Hi Edmond.
It will ultimately depend on the amplifier topology, but the loss of gain will be at LF and is pretty much inconsequential (if the VAS is loaded lightly with, say, a triple EF, the OLG will be stratospheric at DC anyway), so I disagree that the loss of gain has to be compensated for at all.
The only real detriment is the higher current swing required of the LTP's and the higher distortion this incurs in these stages.
Edmond Stuart said:
Hi Edmond.
It will ultimately depend on the amplifier topology, but the loss of gain will be at LF and is pretty much inconsequential (if the VAS is loaded lightly with, say, a triple EF, the OLG will be stratospheric at DC anyway), so I disagree that the loss of gain has to be compensated for at all.
The only real detriment is the higher current swing required of the LTP's and the higher distortion this incurs in these stages.
Re: Re: Cmcl
C'mon Glen, gain = gain, period, basta, finito.
If a crippled the VAS in this amp
http://www.diyaudio.com/forums/showthread.php?postid=1364947#post1364947
with 2k2, the THD20 is 16 times higher.
BTW, I'm glad Rachel is back.
Cheers, Edmond.
G.Kleinschmidt said:
C'mon Glen, gain = gain, period, basta, finito.
If a crippled the VAS in this amp
http://www.diyaudio.com/forums/showthread.php?postid=1364947#post1364947
with 2k2, the THD20 is 16 times higher.
BTW, I'm glad Rachel is back.
Cheers, Edmond.
Re: Re: Re: Cmcl
I'm not arguing that the distortion isn't higher, I'm saying that attempting to compensate for the reduced OLG with an additional stage won't improve the THD-20 (it only has potential to make it worse, as another imperfect stage is added).
Anyway, is that a differential to single ended input amplifier board I see in the pictures above?
I've bettered 1ppm THD-20 in sim with a bridged version of my own "crippled VAS" topology using a hybrid phase splitter with valves in it. I'm building it now.
Cheers,
Glen
PS
I only took miss Weisz back because she begged me to.
Edmond Stuart said:
C'mon Glen, gain = gain, period, basta, finito.
If a crippled the VAS in this amp
http://www.diyaudio.com/forums/showthread.php?postid=1364947#post1364947
with 2k2, the THD20 is 16 times higher.
BTW, I'm glad Rachel is back.
Cheers, Edmond.
I'm not arguing that the distortion isn't higher, I'm saying that attempting to compensate for the reduced OLG with an additional stage won't improve the THD-20 (it only has potential to make it worse, as another imperfect stage is added).
Anyway, is that a differential to single ended input amplifier board I see in the pictures above?
I've bettered 1ppm THD-20 in sim with a bridged version of my own "crippled VAS"
topology using a hybrid phase splitter with valves in it. I'm building it now.Cheers,
Glen
PS
I only took miss Weisz back because she begged me to.
Re: Re: Re: Re: Cmcl
Not yet, that will be the next addition. The design is ready and tested (it's based on Bruno Putzey's differential amp published as Convention Paper 6294 at the 117th Convention 2004 October 28–31 San Francisco, CA, with some improvements (output stage, servo, modified compensation, etc...), the PCB design is about to be sent to the manufacturer. I still have to decide on a single ended to balanced configuration (slide?) switch which is so far not installed on the back panel.
What you see in the above picture are the two OPS attached to heatsinks, two front end boards, two power supply boards with power sequencing (under the OPSs), right between the front end boards the protection circuitry (fans control, thermal shutdown, overload/clipping, output offset, anti-pop/click circuitry) and not really visible in the front compartment the mains transformers soft start (triac based) and the amp soft start (front panel pushbutton activated).
G.Kleinschmidt said:
Not yet, that will be the next addition. The design is ready and tested (it's based on Bruno Putzey's differential amp published as Convention Paper 6294 at the 117th Convention 2004 October 28–31 San Francisco, CA, with some improvements (output stage, servo, modified compensation, etc...), the PCB design is about to be sent to the manufacturer. I still have to decide on a single ended to balanced configuration (slide?) switch which is so far not installed on the back panel.
What you see in the above picture are the two OPS attached to heatsinks, two front end boards, two power supply boards with power sequencing (under the OPSs), right between the front end boards the protection circuitry (fans control, thermal shutdown, overload/clipping, output offset, anti-pop/click circuitry) and not really visible in the front compartment the mains transformers soft start (triac based) and the amp soft start (front panel pushbutton activated).
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