USB5012 USB8741 design update.
Hi,
::USB5102 DAC card using the new TI PCM5102 chip::
I have finished work on the USB5102 dac card and will be ordering a number of boards today or tomorrow. I do not expect any problems with the card as it reuses 90% of the proven USB9023 schematic and layout. I have been told the 'nik' branch of the code supports 32bit sooooo there is the possibility of 32b/192k. I don't provide software or support so don't rain down rocks on me it the statement proves false.
There is a small change to the output connections to accommodate a builder request. The RCA connectors have been swapped for a model that has a gold plating option. I won't be supplying gold connectors but you can buy them from Mouser. There is also a 3.5mm jack to eliminate the need for a 'Y' cable.
::USB8751 DAC card using the Wolfson WM8741 chip::
The hardware is finished and I have locked the schematic and board layout. The USB8741 will not come with an I/V stage and it is up to the builder to provide that functionality.
The USB8741 is different from the 2 designs already released which have no user configurable parameters. (well not via software) The WM8741 supports user configuration of a number of parameters via a I2C bus. A module for user configuration parameters needs to be written as well as an application running on the PC to push these values into the device.
Once I have populated and running USB5102 card I will turn my focus on the firmware and software needed to support the WM8741. Since the USB8741 without the firmware and software just burns electricity I won't be offering kits until the firmware and software is proven.
Full document archives are available at from the appropriate links at
Yoyodyne Consulting/Audio Hardware
Back to the drawing board.....
George
Hi,
::USB5102 DAC card using the new TI PCM5102 chip::
I have finished work on the USB5102 dac card and will be ordering a number of boards today or tomorrow. I do not expect any problems with the card as it reuses 90% of the proven USB9023 schematic and layout. I have been told the 'nik' branch of the code supports 32bit sooooo there is the possibility of 32b/192k. I don't provide software or support so don't rain down rocks on me it the statement proves false.
There is a small change to the output connections to accommodate a builder request. The RCA connectors have been swapped for a model that has a gold plating option. I won't be supplying gold connectors but you can buy them from Mouser. There is also a 3.5mm jack to eliminate the need for a 'Y' cable.
::USB8751 DAC card using the Wolfson WM8741 chip::
The hardware is finished and I have locked the schematic and board layout. The USB8741 will not come with an I/V stage and it is up to the builder to provide that functionality.
The USB8741 is different from the 2 designs already released which have no user configurable parameters. (well not via software) The WM8741 supports user configuration of a number of parameters via a I2C bus. A module for user configuration parameters needs to be written as well as an application running on the PC to push these values into the device.
Once I have populated and running USB5102 card I will turn my focus on the firmware and software needed to support the WM8741. Since the USB8741 without the firmware and software just burns electricity I won't be offering kits until the firmware and software is proven.
Full document archives are available at from the appropriate links at
Yoyodyne Consulting/Audio Hardware
Back to the drawing board.....
George
The one issue I have with the existing AB1.1 is the noise when switching clock domains. It appears that the crystal oscillators do not start instantly and you get an ugly buzz in the output for a moment (100mS?) when switching clock trains. Perhaps a mute output that mutes the audio stream when changing clocks is all that is required to fix this. otherwise it all works fine on Widows 7, Windows XP, and Linux with the latest ALSA installed.
The I2C interface could be used with some DAC chips to drive the internal volume control. The volume mixer interface seems to be part of the UAC standard so no coding at the driver or application level would be required.
If you need to download code to the chip to enable it there already is a lot available in the Alsa stuff for different DAC chips. There will be more since the biggest OS today in raw numbers (Android) uses Alsa.
Hi Demian, Borge et al,
I have uploaded the latest firmware tweaks to try to mute playback during freq changes. Please test and see whether it works. (I can't test as I have not encountered the problem at all. I use mpd in Linux and any freq change occurs during silence between tracks.)
Alex
I have uploaded the latest firmware tweaks to try to mute playback during freq changes. Please test and see whether it works. (I can't test as I have not encountered the problem at all. I use mpd in Linux and any freq change occurs during silence between tracks.)
Alex
thats good, because its a voltage out dac =) only needs a buffer/filter, but can be used directly if desired (not my choice)
yes, an obvious mistake. I will lie and say I was thinking of the ES9012 while writing.
Folks.
Are you guys also considering multichannel USB-I2S in the near future? (Not sure if I was asking this before).
If yes. Please make sure that it is Linux standard driver compliant.
I'd guess the community (including me of course) really want such a device to finally be able to design great active setups using brutefir.
6*24/96 would be more then sufficient for the beginning.
THX
Are you guys also considering multichannel USB-I2S in the near future? (Not sure if I was asking this before).
If yes. Please make sure that it is Linux standard driver compliant.
I'd guess the community (including me of course) really want such a device to finally be able to design great active setups using brutefir.
6*24/96 would be more then sufficient for the beginning.
THX
Last edited:
6*24/96 would be more then sufficient for the beginning.
THX
Make that 8x24/96 please
ØE
Multi-channel UAC2
Multi-channel UAC2, 8 x 24b/192k, is not possible with the Atmel based USB-I2S subsystem. To have 8 channels you need a processor with 4 I2S channels and enough horsepower to process the volume of data. Add to that requirement you need a robust USB engine with enough endpoints to handle the UAC2 needs.
You can get multi-channel UAC2 with the XMOS processor, their closed source software and a Thesycon windows driver. This is not open-source friendly so we passed on that device.
The only option is a full FPGA implementation of UAC2 with multichannel I2S. Wish lists are easy to draw up but difficult to turn into hardware. The exaU2I is a FPGA device that will give you multi-channel but is also closed source and uses a custom windows driver.
The ultimate goal is a full open source hardware, firmware and UAC2 driver for windows. If you have a open source hardware you can create custom versions for devices that support user access to internal registers or have display capabilities. You are in control and not the marketing department of a multi-national.
If there are any FPGA guru's out there that would like to throw their hat into the ring and work on a Xilinx based UAC2-I2S engine lets us know.
regards
George
Multi-channel UAC2, 8 x 24b/192k, is not possible with the Atmel based USB-I2S subsystem. To have 8 channels you need a processor with 4 I2S channels and enough horsepower to process the volume of data. Add to that requirement you need a robust USB engine with enough endpoints to handle the UAC2 needs.
You can get multi-channel UAC2 with the XMOS processor, their closed source software and a Thesycon windows driver. This is not open-source friendly so we passed on that device.
The only option is a full FPGA implementation of UAC2 with multichannel I2S. Wish lists are easy to draw up but difficult to turn into hardware. The exaU2I is a FPGA device that will give you multi-channel but is also closed source and uses a custom windows driver.
The ultimate goal is a full open source hardware, firmware and UAC2 driver for windows. If you have a open source hardware you can create custom versions for devices that support user access to internal registers or have display capabilities. You are in control and not the marketing department of a multi-national.
If there are any FPGA guru's out there that would like to throw their hat into the ring and work on a Xilinx based UAC2-I2S engine lets us know.
regards
George
I fully understand the comment about needing 4 I2S channels, but I am confused about multiple endpoints for UAC2. I have the UAC specifications; can you point to the sections that describe multiple endpoints? I was under the impression that output of 8 channels would still be handled by a single endpoint, albeit a High Speed Isochronous endpoint with more than 1024 bytes per frame. I'd like to understand this better.
Yep, I'm quite familiar with High Speed USB 2 High Bandwidth Isochronous endpoints. But you don't need more than one of these endpoints in a given direction, which is why I was confused by M. Boudreau's comments.
Ah, that makes sense.
I'm accustomed to designing with processors (PIC, TMS320) that support 8 or 16 endpoints, so 3 ISO endpoints is no problem. If the ATMEL is underpowered and the XMOS is proprietary, then perhaps a design based around the TMS320C5535 would be very useful. The firmware development would be significant, but not impossible.
I have experience designing hardware and firmware with the TMS320VC5506, which uses the Texas Instruments CSL (Chip Support Library) for USB. Unfortunately, that is only a Full Speed Device. Some elements of ISO endpoints must be written by the firmware developer, but the basic hardware support is there for anything that is legal. They have separate documents to describe the USB hardware and USB library. We'd have to find the corresponding documents for the C5533/C5534/C5535.
They do point out that the C553x does not support Host Mode, on-chip charge pump, or OTG. In other words, they do not specifically exclude the high bandwidth ISO transfer features of standard USB 2.0 High Speed. But it would still be good to confirm. The E2E (Engineer to Engineer) Forum at TI might be a good place to ask if the hardware/library documentation is not explicit.
Note, it has 10 EPs if you count the Control IN and Control OUT, but you probably noticed that.
Hi Alex,
I'm playing with this code now on the audio-widget-nik branch, compiled locally using make-widget-win7. Things sound nice. The only issue I (still) notice is that there is a chirp like sound when I skip between songs in some Windows players, particularly VLC. But that only occurs on UAC1, not UAC2. It is more prominent in our firmware than on other UAC1 devices I have tried with the same player and music. Content is Crash Test Dummies 16/44.1 ripped to MP3.
The chirps are _not_ the same for every skip. What it sounds like to me is the last few ms being played back a few times. Tonal pitch is the same. So my question is: Is there a buffer or FIFO which is played again and again, and which is NOT cleared if some sort of sync is lost? (Or perhaps during a sample rate change?) And is this sort of mechanism different in UAC1 and UAC2?
I know it is a poorly stated question. I'm waiting for a proper dig scope which would have shown you what I'm referring to in the time domain.
Børge
I'm playing with this code now on the audio-widget-nik branch, compiled locally using make-widget-win7. Things sound nice. The only issue I (still) notice is that there is a chirp like sound when I skip between songs in some Windows players, particularly VLC. But that only occurs on UAC1, not UAC2. It is more prominent in our firmware than on other UAC1 devices I have tried with the same player and music. Content is Crash Test Dummies 16/44.1 ripped to MP3.
The chirps are _not_ the same for every skip. What it sounds like to me is the last few ms being played back a few times. Tonal pitch is the same. So my question is: Is there a buffer or FIFO which is played again and again, and which is NOT cleared if some sort of sync is lost? (Or perhaps during a sample rate change?) And is this sort of mechanism different in UAC1 and UAC2?
I know it is a poorly stated question. I'm waiting for a proper dig scope which would have shown you what I'm referring to in the time domain.
Børge