New XMOS usb 384khz

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Have you guys ever thought that if passing a clock signal through a lowly flip flip already adds a certain amount of jitter, and FPGA people states that at a minimum an FPGA will add 100 psec of period jitter (equivalent to ~10-15 psec of phase jitter),

When a clock signal goes into a DAC through its interface circuitry, jitter is immediately added.

Is there a need to use ultra low phase noise clocks in the sub psec range?
 
Have you guys ever thought that if passing a clock signal through a lowly flip flip already adds a certain amount of jitter, and FPGA people states that at a minimum an FPGA will add 100 psec of period jitter (equivalent to ~10-15 psec of phase jitter),

When a clock signal goes into a DAC through its interface circuitry, jitter is immediately added.

Is there a need to use ultra low phase noise clocks in the sub psec range?

Yes and agree! All Modern DAC including ES9018(syn mode) uses MCK to interpolate / clock in the i2s data(as refer to rsowen and many DAC chip level designer), ps amount of jitter in the I2S bus will not affect sound quality. Add flip flip or other circuit to reclock in the I2S will only add more noise or affect the i2s bus data integrity

For NOS or decade old DAC (TDA1541 etc) which do not need MCK, they are the only device affected by the jitter in the I2S seriously and reclock on i2s's advantage is larger than disadvantage.

The XMOS approach is far better than other usb to i2s solution(such as cm6631/a, mck are from cm6631/a and not from oscillator directly)
I am looking to see more other xmos i2s solution is available on the market:cool: It's not only the best and it's also the most simple solution to use computer listen high quality music
 
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Hi Diyinhk:
Why you think CM6631/CM6631A MCK not from oscillator directly? Do you have document or some thing to prove it?


Yes and agree! All Modern DAC including ES9018(syn mode) uses MCK to interpolate / clock in the i2s data(as refer to rsowen and many DAC chip level designer), ps amount of jitter in the I2S bus will not affect sound quality. Add flip flip or other circuit to reclock in the I2S will only add more noise or affect the i2s bus data integrity

For NOS or decade old DAC (TDA1541 etc) which do not need MCK, they are the only device affected by the jitter in the I2S seriously and reclock on i2s's advantage is larger than disadvantage.

The XMOS approach is far better than other usb to i2s solution(such as cm6631/a, mck are from cm6631/a and not from oscillator directly)
I am looking to see more other xmos i2s solution is available on the market:cool: It's not only the best and it's also the most simple solution to use computer listen high quality music
 
Eventually NDK released an easy-reading document that illustrated an importance of low phase noise oscillators in consumer audio applications, today on their website. The document is written in Japanese only. However, you can look at a figuare of phase noise plots of their typical products.
The title in Kanji characters means "Phase Noise Comparison of Crystal Oscillators".

004.png


The OCXO type referenced in the graph above is used in a TAD CD player.

NZ2520SD is out of stock in chip1stop immediately:eek: Anybody has chance to try and told us the result:p
 
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Here is XMOS on Taobao. It show jitter at 4.6ps. It is Taobao, so maybe fake. But I think it is good to share, fake or no.

XMOS USBÒì²½´«ÊäÊý×ֽӿڰ壬jitterµÍÖÁ4.6ps£¬ÃëɱCM6631A-ÌÔ±¦Íø

And here is beauty.

XMOS 384k-USB-AUDIOÊý×Ö½Ó¿Ú½çÃæ usbתͬÖá-ÌÔ±¦Íø

Can Diyinhk U6A XMOS & driver have more than one XMOS for multi-channel ?

Actually, I am doing what I will use:p and I think the best can only be done like this. I always use computer and headphone to listen music.
For SPDIF, I will use CM6631 for AC3/DTS-passthru when playing concert DVD to my yamaha AV amp. As I know, xmos do not support SPDIF AC3/DTS-pass through currently. I also want to know if there is any plan on support AC3/DTS passthru SPDIF and DSD i2s in official firmware source:Dcode.

Hi...

I can make P/N varification of the nz2520sd If i can get samples.

hope nz2520sd will re-stock soon
 
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Ok, not fake. But this is not special for MCLK but ok only.

The 4.6ps MCLK is measured directly from the xmos reference board crystal with nc7wzu04 to form an oscillator circuit, after pass through NC7sZ157 and NC7WZ17 buffer. It's not fake but clearly unrelated if some circuit is using other oscillator.

Did you request "QUOTE" for the part number input of;
NZ2520SD-22.579200M-NSA3449C
NZ2520SD-24.576000M-NSA3449C
and did their quote replies after a couple days later say "out of stock"?

You always need to request "QUOTE" and wait for their reply.

thanks, I will definitely try to get some to play:D NZ2520SD should be the lowest noise oscillator for audio
 
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... It seams that chip1stop has no NZ2520SD in the 24.576 or 22.5792MHz

I will instead order 1pcs @ 25MHz at make the varification of this. Does anybody have any comment to this? ...

Have you made inputs of the following part numbers and request "QUOTE" by clicking the button? You need your registration to get a quote.

NZ2520SD-22.579200M-NSA3449C
NZ2520SD-24.576000M-NSA3449C

Did their estimate replies after a couple days later say "out of stock"?
 
why does he always put decoupling caps so far away?

hmm I would be interested to see how longer non impedance controlled and yes..inductive traces compare to the inductance caused by directly connecting with a micro via.

Disagree.
microvia resistance negligable and for decoupling is imaterial, it is inductance that is the concern (approx 0.0004 Ohms).
4 layers would allow for interplane capacitance on the power pair, improving decoupling, this would improve the decoupling further and would allow more room to optimise routing. Also it would improve the impedance of the power supply to the pins of the device and the decoupling caps.
This would also allow for a decent ground plane directly under the top layer optimising signal transmission. For the difference in cost you would get a much better product, and more in keeping with a higher end audio image.
Microvias would be a bit of overkill for this design, but personaly I would feal better parting with my money if it was a 4 layer design. Even nicer but costly would be a HDI design with outer layers all ground and signal burried on the first layer down.
All that said the simplicity of the design allows it to be done on two layers and work, the above points I made are just going the liitle bit extra for the best signal integrity.

After all, qusp is right about XMOS in general and your poorly made product in special (layout, decoupling, switching mode PSUs?). My 2 cents..

Thank you for many diyer asking about the decoupling cap distance:rolleyes:
A photo with a ruler is used for better visual understanding. The current design is 2mm from the chip, if you find your design has decoupling cap longer than 2mm distance is considered to be too long and poorly design:D Diyer are always like to testing the limit, it will be moved to 1mm from chip in the next version:) instead, micro via has inductance and the board thickness(1-1.6mm typically) decouple cap distance length. With 1mm length and trace to groudplane capacitance, it should provide better result than microvia easily:eek:

Any suggestion and improvement are always welcome!

An externally hosted image should be here but it was not working when we last tested it.
 
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