My implementation of the Cordell Distortion Analyser

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Thank you, this is very helpful.

Measured distortion level is essentially independent from the input level to the analyzer; in fact, it goes down somewhat at higher input levels, which is probably due to noise.

It is also independent from the level set by the agc in the oscillator.

I did measure distortion levels at the three outputs of the oscillator. It is 0.004% after the second integrator, 0.012% after the first, and 0.025% at the output of the inverter. 10dB down after each integrator corresponds to the 3rd harmonic I see on the scope. Interestingly, the distortion level changes very little when I bring the agc rectifier out of balance.

I could not observe any ripple in the control signal from IC7 driving the FET.

So it looks like the FET is to be suspected. I could not find 2N4091s or any other FET with both high Vgs off and low Rds on, so I used 2SK170, which has low Rds on (40 ohm) and low Vgs off (.7V). I'll try to change is to something more suitable.
 
Thank you, this is very helpful.

Measured distortion level is essentially independent from the input level to the analyzer; in fact, it goes down somewhat at higher input levels, which is probably due to noise.

It is also independent from the level set by the agc in the oscillator.

I did measure distortion levels at the three outputs of the oscillator. It is 0.004% after the second integrator, 0.012% after the first, and 0.025% at the output of the inverter. 10dB down after each integrator corresponds to the 3rd harmonic I see on the scope. Interestingly, the distortion level changes very little when I bring the agc rectifier out of balance.

I could not observe any ripple in the control signal from IC7 driving the FET.

So it looks like the FET is to be suspected. I could not find 2N4091s or any other FET with both high Vgs off and low Rds on, so I used 2SK170, which has low Rds on (40 ohm) and low Vgs off (.7V). I'll try to change is to something more suitable.

Hi Alex,

This is good information. It does sound like the AGC FET may be to blame. It is odd, however, that adjusting the oscillator agc to obtain a higher operating signal level in the oscillator does not increase distortion, including any that would be introduced by the agc FET. I know the 2N4091 is no longer available, and that is problematic. Its high Vgs off is important to minimize its distortion contribution, as the operating signal is then small compared to Vgs. I'm surprized that there are not any good substitutes out there.

Of course, we cannot fully rule out that there is some other source of distortion, such as bad op amps or op amps that are oscillating. What op amps are you using? Maybe try another, like the LM4562, that is internally compensated for unity gain.

It is entirely possible to replace the JFET agc with a good low-noise analog multiplier with some good engineering.

Best,
Bob
 
I wonder if it is easier to find a suitable part or to build a variation of the oscillator with a multiplier instead of the FET.

Actually the JFET *is* part of a multiplier; commercially available multipliers (e.g. AD633) don't offer sufficiently low distortion/noise (though you could roll-your-own if you know how). A J111 should be a decent replacement for the 2N4091 and easy to source.

Samuel
 
Actually the JFET *is* part of a multiplier; commercially available multipliers (e.g. AD633) don't offer sufficiently low distortion/noise (though you could roll-your-own if you know how). A J111 should be a decent replacement for the 2N4091 and easy to source.

Samuel

Hi Samuel,

Thanks for pointing out the possible J111 alternative to the 2N4091.

With regard to the use of an analog multiplier, things may not be as bad as you suggest. The reason for this is that the JFET or multiplier is only manipulating a small amplitude correction signal. If using a multiplier, one would operate it at a level where the tradeoff between its distortion and its noise was optimum, and then attenuate the ouput of the multiplier before it is injected into the summing node. I have not tried this, but I think it is a promising approach.

On the other hand, if one used multipliers directly in the signal path, such as to replace the stepped tuning resistors, then the distortion and noise of the multiplier would really get you.

Cheers,
Bob
 
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Samuel, Bob: thank you again for your advice.

Unfortunately, J111 are not easily available locally, so following the discussion, I replaced the three FETs in the agc of the oscillator and in the gain and frequency controls of the filter with 2SK246 (Vgs off = 7 volts, Rds on = 350 ohm) and adjusted the associated resistor networks to keep the gain of the multipliers within +/-0.3V/V and the voltage across the FETs at 40mVrms. Also, I corrected an instability with one of the LM318s. My measurement floor now is at 0.001%, and the residual now is mostly the fundamental - I guess the gain and frequency nulls of the auto tuning circuit need adjustment. The floor improves at higher levels, so FETs now are not an issue. Now it looks promising.

As for the multipliers, I was thinking about using either AD633 or MPY634 along the lines Bob suggest. As the default gain function for both is X*Y/10+Z, it seems to be possible to plug them directly in place of the FET+opamp, removing the restriction for the control voltage to go positive. +/-3V of control voltage would then result in the same gain a FET+opamp provide in the original circuit.
 
I replaced the three FETs in the agc of the oscillator and in the gain and frequency controls of the filter with 2SK246 (Vgs off = 7 volts, Rds on = 350 ohm) and adjusted the associated resistor networks.

You could also parallel multiple FETs to get something similar to a 2N4091.

With regard to the use of an analog multiplier, things may not be as bad as you suggest. The reason for this is that the JFET or multiplier is only manipulating a small amplitude correction signal. If using a multiplier, one would operate it at a level where the tradeoff between its distortion and its noise was optimum, and then attenuate the ouput of the multiplier before it is injected into the summing node. I have not tried this, but I think it is a promising approach.

I've done considerable amount of research in very low distoriton oscillators (at the -140 dB level) the last year, so I've probably become somewhat too critical. Still I believe that it won't be easy to use standard multipliers--they're just so noisy. The AD633 outputs -76.7 dBu in a 20 kHz bandwidth so it will need serious decoupling. This again means that it cannot be operated at too low level or its authority will be too low for fast settling (or any amplitude stability at all). But I'd need to do some math to see how things really are.

Samuel
 
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Samuel,

I hear what you saying about analog multipliers.

Just out of curiosity, have you looked in your research at VCAs such as SSM2018 or LT1228? The first was used by Cyril Bateman in the instrument he used to measure capacitor distortion ("Capacitor Sound", Electronics World, July 2002 - January 2003, a copy is available at Scribd). His oscillator gave distortion of parts-per-million. The datasheet for SSM2018 says the THD is 0.006%. The other chip was used in the AGC loop of the oscillator from Linear Technology's Application Note AN-67, the measurement of distortion of which was said to "defy all the author's resources, but appearing to be well into the parts-per-billion range". The datasheet for LT1228 says THD is 0.2%.

Alexey
 
Just out of curiosity, have you looked in your research at VCAs such as SSM2018 or LT1228?

Yes. Basically you have to appreciate that a VCA is not a full four-quadrant multiplier but rather a two-quadrant multiplier. At high frequencies (> 10 kHz) the multiplier might actually need to dampend rather than enhance the Q of a state-variable filter because of opamp phase shift contributions (I don't know about the HF behaviour of other oscillator topologies). This means that a single VCA will not achieve amplitude stability. The oscillators you mention are both working at a comparably low and single frequency which does avoid the need for a four-quadrant multiplier (furthermore the Linear oscillator uses a trim to adjust the Q).

One can combine two VCAs such that their summed output gives full four quadrant operation. However there is another limitation: for fast settling, guaranteed amplitude stability and easy design of the AGC loop we want a linear multiplier gain law--VCA have a dB-linear law. Again this is much less of a problem for a single-frequency design as the operating conditions of the multiplier are tightly controllable.

Distortion/noise of an audio VCA would surely be adequate if properly applied. I don't think the LT1228 is a particularly clever choice though (they just had to use LT parts I guess)--it must be operated at very low AC voltage for acceptable linearty which results in high noise. Indeed some measurements of this oscillator I've seen indicate rather high noise levels.

BTW I doubt the Linear oscillator achieves the distortion levels they claim. I presume that the very nonlinear wiper resistance of the trim pot limits things to about -140 dB.

Samuel
 
BTW I doubt the Linear oscillator achieves the distortion levels they claim. I presume that the very nonlinear wiper resistance of the trim pot limits things to about -140 dB.

Samuel

The Linear Super Oscillator's distortion is on the order of my Krohn Hite 4400 and AP Analog Generators. It has to be in a steel tin and battery operated, else it picks up any manner of RFI/EMI.
 
With regard to the use of an analog multiplier, things may not be as bad as you suggest. The reason for this is that the JFET or multiplier is only manipulating a small amplitude correction signal. If using a multiplier, one would operate it at a level where the tradeoff between its distortion and its noise was optimum, and then attenuate the ouput of the multiplier before it is injected into the summing node. I have not tried this, but I think it is a promising approach.

Hi Bob,

I've been working on this approach for the last few months, and it seems very promising indeed. My fixed-frequency prototype (1 kHz) employs three analog multiplier (two in the sin^2+cos^2 rectifier and the last one in the Q-controlling loop - all AD633) and either I'm doing something completely wrong or its THD is very low: the 2nd harmonic sits around ~-130 dB, the 3rd below ~-135 dB and the 5th below ~-140 dB (@ +6dBV out) - the other ones are below the noise floor of my analysers. After trying a few topologies I've assembled a couple of them just to test my generator: an auto-tuning SVF-based notch (I've learned a lot from your beautiful work) and a fixed-frequency double-notch built around a Bainter notch followed by a Twin-T one (both analysers employ a bunch of ultra-low THD LME49720 opamp from National). Though it's actually possibile that what I'm seeing is some kind of THD cancellation, it would seem quite strange for two completely different notch topologies to behave the same way in cancelling out distortion products - actually the results I get from the SVF notch and the Bainter/Twin-T double-notch are in very good agreement (the levels of measured 2nd, 3rd and 5th harmonics differ by less than 1.5 dB). Direct measurements with my EMU0202 yelds a THD value of <0.0005% (@44kHz sampling rate), i.e. near the lower limit of the card or just beyond it.

I'm still not 100% sure about the results I get, but I think that reaching such a low THD level is actually possible thanks to both the almost unmeasurable level of ripple from the rectifying stage (~-120 dBV @ 2 kHz and +10dBV out) and the Q controlling multiplier operating at very low amplitude levels (and the high operating Q of the SVF topology, of course).

Ciao,

Luca
 
That sounds like a decent oscillator. What amplitude settling time do you achive? What's the amplitude noise/sideband performance?

As I said a fixed frequency oscillator is *much* simpler to design than something which covers the 10 Hz-100 kHz range. My comment with respect to the unsuitability of the AD633 was strictly meant for such and also assumes the need for fast amplitude settling.

Samuel
 
BTW to increase the confidence of your measurements at this level you could verify the distortion at all three outputs of the state variable ring as well as at the multiplier output. For my oscillator design I get -135 dB for the 2nd and 3rd harmonic (no higher harmonics measurable) at all three oscillator outputs which gives some confidence that this is actually an analyzer contribution.

For a fixed frequency oscillator it is in fact much simpler to just add e.g. a Chebyshev low pass filter at the oscillator output rather than spending too much efforts in reducing level detector ripple and multiplier distortion.

Samuel
 
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My apologies for the repeated posts...

Almost unmeasurable level of ripple from the rectifying stage (~-120 dBV @ 2 kHz and +10 dBV out).

Just to make sure: 2nd harmonic content in the ripple causes 3rd harmonic in the oscillator output because this is an amplitude modulation process where harmonic distortion appears as difference frequency. Often the limiting ripple content is at the fundamental frequency (i.e. 1 kHz in your case, caused by multiplier control voltage feed through) which causes 2nd harmonic distortion in the oscillator output which is well less rejected than 3rd harmonic (just 9.5 dB instead of 18 dB).

Samuel
 
That sounds like a decent oscillator. What amplitude settling time do you achive? What's the amplitude noise/sideband performance?

As I said a fixed frequency oscillator is *much* simpler to design than something which covers the 10 Hz-100 kHz range. My comment with respect to the unsuitability of the AD633 was strictly meant for such and also assumes the need for fast amplitude settling.

Samuel

You're right, it's fixed frequency 10kHz -- the CFB opamps have oodles of gain. The amplitude runs to 5V at it's best and the noise seems down in the lowhundreds of nanoVolts. I should run the tests again since I've acquired an AP analyzer. In fairness, this is not what I would call a really robust instrument since it needs to be adjusted each and every time you use it.

The Boonton 1120 takes a few seconds to settle on each frequency -- the frequency is automatically adjusted to an internal counter so there is some hesitation in getting its THD down below 0.0008%
 
BTW to increase the confidence of your measurements at this level you could verify the distortion at all three outputs of the state variable ring as well as at the multiplier output. For my oscillator design I get -135 dB for the 2nd and 3rd harmonic (no higher harmonics measurable) at all three oscillator outputs which gives some confidence that this is actually an analyzer contribution.

Hi Samuel, I just did a couple of tests with both analysers - using the Bainter/Twin-T double notch I get a fixed ~-140 dB 3rd harmonic residual, while the 2nd harmonic level varies between ~-127 dB (HP out) and ~-140 dB (LP out); the 2nd harmonic from the BP out is ~3 dB higher (~-137 dB), which sounds a little bit strange. The SVF auto notch is considerably noisier: the 3rd harmonic is consistently beyond noise floor, while 2nd harmonic level lowers almost exactly by 6dB/oct switching from HP (~-126dB) to BP (~-132dB); the 2nd harmonic from the LP output is buried in the noise.

For a fixed frequency oscillator it is in fact much simpler to just add e.g. a Chebyshev low pass filter at the oscillator output rather than spending too much efforts in reducing level detector ripple and multiplier distortion.

Samuel[/QUOTE]
 
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