Hi
I see you did you background check
, yeah the package is very touchy to work with its clocking at 300MHZ so layout is an issue, I have two ADAU1452`s laying on a antistatic matt no where near ready to use them. Are you sure the emulator cable will work? dont they use a propriety protocol over I2C and SPI ?? its on the 8051 processor on the cirris logic usbi cable.. uhmm
by the way my sharc, blackfin emulator is arriving soon so I will be looking to developing for the sharc and blackfin platform im interested in other dsp aspecs like echo cancellation, fx, reverbs and image detection
I like this thread keep up the good work! are you on IM I would like to get in touch with people in this area of study.
Great thread. Anyway regardin the ADAU1452 would it be possible to just glue the chip at thermal pad using Arctic Silver Thermal Adhesive (with 7.5 watts/m°C vs. about 30 of tin solder, 1/4 is a lot less but might be enough)? I don't think soldering the 50 mil pins using iron is your biggest problem there.
Last edited:
Last week I was doing a bit of homework and looked around for a SMD Rework station while on a budget...
Read a few positive reviews on the Xpower 992DA+ and pulled the trigger.
Bought it off eBay from a reputable seller and paid $100 plus another $25 for shipping.
Unit showed up today and way mucking about with it for a while.
I do have to say im quite impressed with it and works out of the box as advertised!
Picked up a old cable box i had kicking around and tore into it...
MAN... Isn't life easier when you have the proper tools !! LOL
I was pulling TSOP's, SOIC's and BGA's like it was no ones business !
I could not believe how easy it was... in fact I even got my 10 year old daughter try it with minimal instruction and she did it without even lifting a trace.
Here's the box of parts we lifted off the board ( me and my daughter - she really likes this and thinks its fun )
Read a few positive reviews on the Xpower 992DA+ and pulled the trigger.
Bought it off eBay from a reputable seller and paid $100 plus another $25 for shipping.
Unit showed up today and way mucking about with it for a while.
I do have to say im quite impressed with it and works out of the box as advertised!
Picked up a old cable box i had kicking around and tore into it...
MAN... Isn't life easier when you have the proper tools !! LOL
I was pulling TSOP's, SOIC's and BGA's like it was no ones business !
I could not believe how easy it was... in fact I even got my 10 year old daughter try it with minimal instruction and she did it without even lifting a trace.
Here's the box of parts we lifted off the board ( me and my daughter - she really likes this and thinks its fun )
Not much going on right now...
Work picked up a bit and had to cut back a bit on the time spent on this project, plus all the routing I did on the DSP trio and DAC was wrecked by Altium Auto Router so now I will have to lay it out again by hand.
Decided to test out the local guy and see how well he fairs as I heard mixed reviews.
So...
I laid out a single DAC and will have him make me a few boards.
These are "universal" as they can have all In's and Out's routed to the board edge.
The DAC out is NOT buffered and figured that would be the best left to the End Users liking whetever you want Active or Passive Buffers. The control was laid out in such a way that both I2C and SPI can be used by the means of jumpers and even pull-up resistors are on board for I2C. Clock can be Generated on Board or fed by a secondary source like a DSP, again selectable by the means of a jumper.
Work picked up a bit and had to cut back a bit on the time spent on this project, plus all the routing I did on the DSP trio and DAC was wrecked by Altium Auto Router so now I will have to lay it out again by hand.
Decided to test out the local guy and see how well he fairs as I heard mixed reviews.
So...
I laid out a single DAC and will have him make me a few boards.
These are "universal" as they can have all In's and Out's routed to the board edge.
The DAC out is NOT buffered and figured that would be the best left to the End Users liking whetever you want Active or Passive Buffers. The control was laid out in such a way that both I2C and SPI can be used by the means of jumpers and even pull-up resistors are on board for I2C. Clock can be Generated on Board or fed by a secondary source like a DSP, again selectable by the means of a jumper.
Revamped the DAC boards and now are sporting UFL connectors versus the male headers that were on there as well a re-designed rest circuit that allows IOVDD to settle to operating level prior to the DSP starting to boot up. This was done as per the Datasheet with a bit of forgery from their Eval board circuit
Also please keep in mind that this 2 layer board is mainly for prototyping purposes!
This way the all the code and software for the DAC Volume Control and Mute function can be generated and tested.
The "Production" / Final board will be a 4 layer board with designated Signal, Ground and Power planes.
PS: Software can be generated automatically inside Sigma Studio using this little guide for the "HOW TO"
Anyway's...
Without further delay, here's the new layouts:
Also please keep in mind that this 2 layer board is mainly for prototyping purposes!
This way the all the code and software for the DAC Volume Control and Mute function can be generated and tested.
The "Production" / Final board will be a 4 layer board with designated Signal, Ground and Power planes.
PS: Software can be generated automatically inside Sigma Studio using this little guide for the "HOW TO"
Anyway's...
Without further delay, here's the new layouts:
The following changes that are coming to this DAC are as follows:
1.- High Precision Oscillator ( going for +-5% or better ) SMD as well
2.- Optional 36 Pin Output header. This would reduce overall board size by 20-30% !
- Current size 86mm x 121mm (3.4" X 4.7) expecting to shrink it to 70mm x 80mm ( 2.75" x 3.14" ) after header placement instead of the multiple plugs.
3.- As mentioned earlier the V3 board will be 4 layer.
4.- SPI will be optional and main form on communication will be I2C.
- The I2C pull up resistors will still be on board, but the headers for it will be omitted.
5.- CLK Select will still bet there just in case you want to use the local clock or output from another source.
6.-
1.- High Precision Oscillator ( going for +-5% or better ) SMD as well
2.- Optional 36 Pin Output header. This would reduce overall board size by 20-30% !
- Current size 86mm x 121mm (3.4" X 4.7) expecting to shrink it to 70mm x 80mm ( 2.75" x 3.14" ) after header placement instead of the multiple plugs.
3.- As mentioned earlier the V3 board will be 4 layer.
4.- SPI will be optional and main form on communication will be I2C.
- The I2C pull up resistors will still be on board, but the headers for it will be omitted.
5.- CLK Select will still bet there just in case you want to use the local clock or output from another source.
6.-
Hi Great job.
Would it be possible to make the layout files for just the DAC board available if your layout turns out OK?
There is discussions on the sursound mailing list about creating a multichannel DAC using a beagleboard Black.
List Sursound is provided for both researchers and producers of multichannel audio as a place to exchange ideas. ()
In Ambisonics and surround with height there is a great need for good quality low cost multichannel DAC's to drive many power amplifiers.
I have 12 speakers in my setup, and up to 20 or more could be of use
48kHz / 24 bits is what I want for my dac's
But a generic good spec DAC can be of use for many applications.
I am thinking of for example of a MADI or Dual ADAT DAC Interface.
Would it be possible to make the layout files for just the DAC board available if your layout turns out OK?
There is discussions on the sursound mailing list about creating a multichannel DAC using a beagleboard Black.
List Sursound is provided for both researchers and producers of multichannel audio as a place to exchange ideas. ()
In Ambisonics and surround with height there is a great need for good quality low cost multichannel DAC's to drive many power amplifiers.
I have 12 speakers in my setup, and up to 20 or more could be of use
48kHz / 24 bits is what I want for my dac's
But a generic good spec DAC can be of use for many applications.
I am thinking of for example of a MADI or Dual ADAT DAC Interface.
I do have a BBB on its way that eventually I will be making a Digital Audio Cape that will also employ a 40 pin ZIF for and LCD/TFT.
For now the SAM3X4E will be the microprocessor of choice for controll
One project at a time tho...
ADHD does kick my @$$ most of the time LOL
When its all and done, everything will be available including 2 versions of the board ( O1 - 16x 3Pin OR O2 Single 36 or 40 Pin Header )
For now the SAM3X4E will be the microprocessor of choice for controll
One project at a time tho...
ADHD does kick my @$$ most of the time LOL
When its all and done, everything will be available including 2 versions of the board ( O1 - 16x 3Pin OR O2 Single 36 or 40 Pin Header )
Last edited:
Well, since I'm on "bedrest" with this nasty flu I might as well get some work done!
Ran downstairs quickly while the wifey went to pick up the kids from school and soldered on a few pins on the LCD so I can hook it up to the Arduino.
Grabbed a few jumpers from my jumper kit and ran back upstairs with the LCD.
wired it up quick, loaded the code onto the due and it works perfect.
Time to go and generate the DAC control file with Sigma Studio
Ran downstairs quickly while the wifey went to pick up the kids from school and soldered on a few pins on the LCD so I can hook it up to the Arduino.
Grabbed a few jumpers from my jumper kit and ran back upstairs with the LCD.
wired it up quick, loaded the code onto the due and it works perfect.
Time to go and generate the DAC control file with Sigma Studio
DAC1.h
DAC1_defines.h
Code:
#ifndef __DAC1_DAC1_H__
#define __DAC1_DAC1_H__
#include "SigmaStudioFW.h"
#include "DAC1_REG.h"
#define DEVICE_ARCHITECTURE_DAC1 "ADAU1966"
#define DEVICE_ADDR_DAC1 0x0
/* Register Default - DAC1.DAC_CTRL0 */
ADI_REG_TYPE R0_DAC_CTRL0_DAC1_Default[REG_DAC_CTRL0_DAC1_BYTE] = {
0x65
};
/* Register Default - DAC1.PLL_CLK_CTRL0 Register.PLL_CLK_CTRL0 */
ADI_REG_TYPE R1_PLL_CLK_CTRL0_DAC1_Default[REG_PLL_CLK_CTRL0_DAC1_BYTE] = {
0x05
};
/* Register Default - DAC1.PLL_CLK_CTRL1 Register.PLL_CLK_CTRL1 */
ADI_REG_TYPE R2_PLL_CLK_CTRL1_DAC1_Default[REG_PLL_CLK_CTRL1_DAC1_BYTE] = {
0x3A
};
/* Register Default - DAC1.PDN_THRMSENS_CTRL_1 Register.PDN_THRMSENS_CTRL_1 */
ADI_REG_TYPE R3_PDN_THRMSENS_CTRL_1_DAC1_Default[REG_PDN_THRMSENS_CTRL_1_DAC1_BYTE] = {
0xB0
};
/* Register Default - DAC1.PDN_CTRL2 Register.PDN_CTRL2 */
ADI_REG_TYPE R4_PDN_CTRL2_DAC1_Default[REG_PDN_CTRL2_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.PDN_CTRL3 Register.PDN_CTRL3 */
ADI_REG_TYPE R5_PDN_CTRL3_DAC1_Default[REG_PDN_CTRL3_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC_CTRL0 Register.DAC_CTRL0 */
ADI_REG_TYPE R6_DAC_CTRL0_DAC1_Default[REG_DAC_CTRL0_DAC1_BYTE] = {
0x65
};
/* Register Default - DAC1.DAC_CTRL1 Register.DAC_CTRL1 */
ADI_REG_TYPE R7_DAC_CTRL1_DAC1_Default[REG_DAC_CTRL1_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC_CTRL2 Register.DAC_CTRL2 */
ADI_REG_TYPE R8_DAC_CTRL2_DAC1_Default[REG_DAC_CTRL2_DAC1_BYTE] = {
0x04
};
/* Register Default - DAC1.DAC_MUTE1 Register.DAC_MUTE1 */
ADI_REG_TYPE R9_DAC_MUTE1_DAC1_Default[REG_DAC_MUTE1_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC_MUTE2 Register.DAC_MUTE2 */
ADI_REG_TYPE R10_DAC_MUTE2_DAC1_Default[REG_DAC_MUTE2_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DACMSTR_VOL Register.DACMSTR_VOL */
ADI_REG_TYPE R11_DACMSTR_VOL_DAC1_Default[REG_DACMSTR_VOL_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC01_VOL Register.DAC01_VOL */
ADI_REG_TYPE R12_DAC01_VOL_DAC1_Default[REG_DAC01_VOL_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC02_VOL Register.DAC02_VOL */
ADI_REG_TYPE R13_DAC02_VOL_DAC1_Default[REG_DAC02_VOL_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC03_VOL Register.DAC03_VOL */
ADI_REG_TYPE R14_DAC03_VOL_DAC1_Default[REG_DAC03_VOL_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC04_VOL Register.DAC04_VOL */
ADI_REG_TYPE R15_DAC04_VOL_DAC1_Default[REG_DAC04_VOL_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC05_VOL Register.DAC05_VOL */
ADI_REG_TYPE R16_DAC05_VOL_DAC1_Default[REG_DAC05_VOL_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC06_VOL Register.DAC06_VOL */
ADI_REG_TYPE R17_DAC06_VOL_DAC1_Default[REG_DAC06_VOL_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC07_VOL Register.DAC07_VOL */
ADI_REG_TYPE R18_DAC07_VOL_DAC1_Default[REG_DAC07_VOL_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC08_VOL Register.DAC08_VOL */
ADI_REG_TYPE R19_DAC08_VOL_DAC1_Default[REG_DAC08_VOL_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC09_VOL Register.DAC09_VOL */
ADI_REG_TYPE R20_DAC09_VOL_DAC1_Default[REG_DAC09_VOL_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC10_VOL Register.DAC10_VOL */
ADI_REG_TYPE R21_DAC10_VOL_DAC1_Default[REG_DAC10_VOL_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC11_VOL Register.DAC11_VOL */
ADI_REG_TYPE R22_DAC11_VOL_DAC1_Default[REG_DAC11_VOL_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC12_VOL Register.DAC12_VOL */
ADI_REG_TYPE R23_DAC12_VOL_DAC1_Default[REG_DAC12_VOL_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC13_VOL Register.DAC13_VOL */
ADI_REG_TYPE R24_DAC13_VOL_DAC1_Default[REG_DAC13_VOL_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC14_VOL Register.DAC14_VOL */
ADI_REG_TYPE R25_DAC14_VOL_DAC1_Default[REG_DAC14_VOL_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC15_VOL Register.DAC15_VOL */
ADI_REG_TYPE R26_DAC15_VOL_DAC1_Default[REG_DAC15_VOL_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.DAC16_VOL Register.DAC16_VOL */
ADI_REG_TYPE R27_DAC16_VOL_DAC1_Default[REG_DAC16_VOL_DAC1_BYTE] = {
0x00
};
/* Register Default - DAC1.CM_SEL_PAD_STRGTH Register.CM_SEL_PAD_STRGTH */
ADI_REG_TYPE R28_CM_SEL_PAD_STRGTH_DAC1_Default[REG_CM_SEL_PAD_STRGTH_DAC1_BYTE] = {
0x20
};
/* Register Default - DAC1.DAC_POWER1 Register.DAC_POWER1 */
ADI_REG_TYPE R29_DAC_POWER1_DAC1_Default[REG_DAC_POWER1_DAC1_BYTE] = {
0xAA
};
/* Register Default - DAC1.DAC_POWER2 Register.DAC_POWER2 */
ADI_REG_TYPE R30_DAC_POWER2_DAC1_Default[REG_DAC_POWER2_DAC1_BYTE] = {
0xAA
};
/* Register Default - DAC1.DAC_POWER3 Register.DAC_POWER3 */
ADI_REG_TYPE R31_DAC_POWER3_DAC1_Default[REG_DAC_POWER3_DAC1_BYTE] = {
0xAA
};
/* Register Default - DAC1.DAC_POWER4 Register.DAC_POWER4 */
ADI_REG_TYPE R32_DAC_POWER4_DAC1_Default[REG_DAC_POWER4_DAC1_BYTE] = {
0xAA
};
/* Register Default - DAC1.DAC_CTRL0 */
ADI_REG_TYPE R33_DAC_CTRL0_DAC1_Default[REG_DAC_CTRL0_DAC1_BYTE] = {
0x64
};
/*
* Default Download
*/
#define DEFAULT_DOWNLOAD_SIZE_DAC1 34
void default_download_DAC1() {
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC_CTRL0_DAC1_ADDR, REG_DAC_CTRL0_DAC1_BYTE, R0_DAC_CTRL0_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_PLL_CLK_CTRL0_DAC1_ADDR, REG_PLL_CLK_CTRL0_DAC1_BYTE, R1_PLL_CLK_CTRL0_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_PLL_CLK_CTRL1_DAC1_ADDR, REG_PLL_CLK_CTRL1_DAC1_BYTE, R2_PLL_CLK_CTRL1_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_PDN_THRMSENS_CTRL_1_DAC1_ADDR, REG_PDN_THRMSENS_CTRL_1_DAC1_BYTE, R3_PDN_THRMSENS_CTRL_1_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_PDN_CTRL2_DAC1_ADDR, REG_PDN_CTRL2_DAC1_BYTE, R4_PDN_CTRL2_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_PDN_CTRL3_DAC1_ADDR, REG_PDN_CTRL3_DAC1_BYTE, R5_PDN_CTRL3_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC_CTRL0_DAC1_ADDR, REG_DAC_CTRL0_DAC1_BYTE, R6_DAC_CTRL0_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC_CTRL1_DAC1_ADDR, REG_DAC_CTRL1_DAC1_BYTE, R7_DAC_CTRL1_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC_CTRL2_DAC1_ADDR, REG_DAC_CTRL2_DAC1_BYTE, R8_DAC_CTRL2_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC_MUTE1_DAC1_ADDR, REG_DAC_MUTE1_DAC1_BYTE, R9_DAC_MUTE1_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC_MUTE2_DAC1_ADDR, REG_DAC_MUTE2_DAC1_BYTE, R10_DAC_MUTE2_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DACMSTR_VOL_DAC1_ADDR, REG_DACMSTR_VOL_DAC1_BYTE, R11_DACMSTR_VOL_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC01_VOL_DAC1_ADDR, REG_DAC01_VOL_DAC1_BYTE, R12_DAC01_VOL_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC02_VOL_DAC1_ADDR, REG_DAC02_VOL_DAC1_BYTE, R13_DAC02_VOL_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC03_VOL_DAC1_ADDR, REG_DAC03_VOL_DAC1_BYTE, R14_DAC03_VOL_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC04_VOL_DAC1_ADDR, REG_DAC04_VOL_DAC1_BYTE, R15_DAC04_VOL_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC05_VOL_DAC1_ADDR, REG_DAC05_VOL_DAC1_BYTE, R16_DAC05_VOL_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC06_VOL_DAC1_ADDR, REG_DAC06_VOL_DAC1_BYTE, R17_DAC06_VOL_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC07_VOL_DAC1_ADDR, REG_DAC07_VOL_DAC1_BYTE, R18_DAC07_VOL_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC08_VOL_DAC1_ADDR, REG_DAC08_VOL_DAC1_BYTE, R19_DAC08_VOL_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC09_VOL_DAC1_ADDR, REG_DAC09_VOL_DAC1_BYTE, R20_DAC09_VOL_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC10_VOL_DAC1_ADDR, REG_DAC10_VOL_DAC1_BYTE, R21_DAC10_VOL_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC11_VOL_DAC1_ADDR, REG_DAC11_VOL_DAC1_BYTE, R22_DAC11_VOL_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC12_VOL_DAC1_ADDR, REG_DAC12_VOL_DAC1_BYTE, R23_DAC12_VOL_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC13_VOL_DAC1_ADDR, REG_DAC13_VOL_DAC1_BYTE, R24_DAC13_VOL_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC14_VOL_DAC1_ADDR, REG_DAC14_VOL_DAC1_BYTE, R25_DAC14_VOL_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC15_VOL_DAC1_ADDR, REG_DAC15_VOL_DAC1_BYTE, R26_DAC15_VOL_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC16_VOL_DAC1_ADDR, REG_DAC16_VOL_DAC1_BYTE, R27_DAC16_VOL_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_CM_SEL_PAD_STRGTH_DAC1_ADDR, REG_CM_SEL_PAD_STRGTH_DAC1_BYTE, R28_CM_SEL_PAD_STRGTH_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC_POWER1_DAC1_ADDR, REG_DAC_POWER1_DAC1_BYTE, R29_DAC_POWER1_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC_POWER2_DAC1_ADDR, REG_DAC_POWER2_DAC1_BYTE, R30_DAC_POWER2_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC_POWER3_DAC1_ADDR, REG_DAC_POWER3_DAC1_BYTE, R31_DAC_POWER3_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC_POWER4_DAC1_ADDR, REG_DAC_POWER4_DAC1_BYTE, R32_DAC_POWER4_DAC1_Default );
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_DAC1, REG_DAC_CTRL0_DAC1_ADDR, REG_DAC_CTRL0_DAC1_BYTE, R33_DAC_CTRL0_DAC1_Default );
}
#endifDAC1_defines.h
Code:
#ifndef __DEFINES_H__
#define __DEFINES_H__
#define BufferSize_DAC1 102
#define NumTransactions_DAC1 34
#endifDAC1_REG.h
And thats all the control code for the DAC.
This maps all the functions of the DSP for the MCU.
All this code was Auto-generated in about 5 Seconds and is ready to be implemented.
Pretty impressive Mr. Analog Devices !
Code:
#ifndef __DAC1_REG_H__
#define __DAC1_REG_H__
/* PLL_CLK_CTRL0 - Registers (DAC1) */
#define REG_PLL_CLK_CTRL0_DAC1_ADDR 0x0
#define REG_PLL_CLK_CTRL0_DAC1_BYTE 1
#define REG_PLL_CLK_CTRL0_DAC1_VALUE 0x5
/* PLL_CLK_CTRL1 - Registers (DAC1) */
#define REG_PLL_CLK_CTRL1_DAC1_ADDR 0x1
#define REG_PLL_CLK_CTRL1_DAC1_BYTE 1
#define REG_PLL_CLK_CTRL1_DAC1_VALUE 0x3A
/* PDN_THRMSENS_CTRL_1 - Registers (DAC1) */
#define REG_PDN_THRMSENS_CTRL_1_DAC1_ADDR 0x2
#define REG_PDN_THRMSENS_CTRL_1_DAC1_BYTE 1
#define REG_PDN_THRMSENS_CTRL_1_DAC1_VALUE 0xB0
/* PDN_CTRL2 - Registers (DAC1) */
#define REG_PDN_CTRL2_DAC1_ADDR 0x3
#define REG_PDN_CTRL2_DAC1_BYTE 1
#define REG_PDN_CTRL2_DAC1_VALUE 0x0
/* PDN_CTRL3 - Registers (DAC1) */
#define REG_PDN_CTRL3_DAC1_ADDR 0x4
#define REG_PDN_CTRL3_DAC1_BYTE 1
#define REG_PDN_CTRL3_DAC1_VALUE 0x0
/* THRM_TEMP_STAT - Registers (DAC1) */
#define REG_THRM_TEMP_STAT_DAC1_ADDR 0x5
#define REG_THRM_TEMP_STAT_DAC1_BYTE 0
#define REG_THRM_TEMP_STAT_DAC1_VALUE 0x0
/* DAC_CTRL0 - Registers (DAC1) */
#define REG_DAC_CTRL0_DAC1_ADDR 0x6
#define REG_DAC_CTRL0_DAC1_BYTE 1
#define REG_DAC_CTRL0_DAC1_VALUE 0x64
/* DAC_CTRL1 - Registers (DAC1) */
#define REG_DAC_CTRL1_DAC1_ADDR 0x7
#define REG_DAC_CTRL1_DAC1_BYTE 1
#define REG_DAC_CTRL1_DAC1_VALUE 0x0
/* DAC_CTRL2 - Registers (DAC1) */
#define REG_DAC_CTRL2_DAC1_ADDR 0x8
#define REG_DAC_CTRL2_DAC1_BYTE 1
#define REG_DAC_CTRL2_DAC1_VALUE 0x4
/* DAC_MUTE1 - Registers (DAC1) */
#define REG_DAC_MUTE1_DAC1_ADDR 0x9
#define REG_DAC_MUTE1_DAC1_BYTE 1
#define REG_DAC_MUTE1_DAC1_VALUE 0x0
/* DAC_MUTE2 - Registers (DAC1) */
#define REG_DAC_MUTE2_DAC1_ADDR 0xA
#define REG_DAC_MUTE2_DAC1_BYTE 1
#define REG_DAC_MUTE2_DAC1_VALUE 0x0
/* DACMSTR_VOL - Registers (DAC1) */
#define REG_DACMSTR_VOL_DAC1_ADDR 0xB
#define REG_DACMSTR_VOL_DAC1_BYTE 1
#define REG_DACMSTR_VOL_DAC1_VALUE 0x0
/* DAC01_VOL - Registers (DAC1) */
#define REG_DAC01_VOL_DAC1_ADDR 0xC
#define REG_DAC01_VOL_DAC1_BYTE 1
#define REG_DAC01_VOL_DAC1_VALUE 0x0
/* DAC02_VOL - Registers (DAC1) */
#define REG_DAC02_VOL_DAC1_ADDR 0xD
#define REG_DAC02_VOL_DAC1_BYTE 1
#define REG_DAC02_VOL_DAC1_VALUE 0x0
/* DAC03_VOL - Registers (DAC1) */
#define REG_DAC03_VOL_DAC1_ADDR 0xE
#define REG_DAC03_VOL_DAC1_BYTE 1
#define REG_DAC03_VOL_DAC1_VALUE 0x0
/* DAC04_VOL - Registers (DAC1) */
#define REG_DAC04_VOL_DAC1_ADDR 0xF
#define REG_DAC04_VOL_DAC1_BYTE 1
#define REG_DAC04_VOL_DAC1_VALUE 0x0
/* DAC05_VOL - Registers (DAC1) */
#define REG_DAC05_VOL_DAC1_ADDR 0x10
#define REG_DAC05_VOL_DAC1_BYTE 1
#define REG_DAC05_VOL_DAC1_VALUE 0x0
/* DAC06_VOL - Registers (DAC1) */
#define REG_DAC06_VOL_DAC1_ADDR 0x11
#define REG_DAC06_VOL_DAC1_BYTE 1
#define REG_DAC06_VOL_DAC1_VALUE 0x0
/* DAC07_VOL - Registers (DAC1) */
#define REG_DAC07_VOL_DAC1_ADDR 0x12
#define REG_DAC07_VOL_DAC1_BYTE 1
#define REG_DAC07_VOL_DAC1_VALUE 0x0
/* DAC08_VOL - Registers (DAC1) */
#define REG_DAC08_VOL_DAC1_ADDR 0x13
#define REG_DAC08_VOL_DAC1_BYTE 1
#define REG_DAC08_VOL_DAC1_VALUE 0x0
/* DAC09_VOL - Registers (DAC1) */
#define REG_DAC09_VOL_DAC1_ADDR 0x14
#define REG_DAC09_VOL_DAC1_BYTE 1
#define REG_DAC09_VOL_DAC1_VALUE 0x0
/* DAC10_VOL - Registers (DAC1) */
#define REG_DAC10_VOL_DAC1_ADDR 0x15
#define REG_DAC10_VOL_DAC1_BYTE 1
#define REG_DAC10_VOL_DAC1_VALUE 0x0
/* DAC11_VOL - Registers (DAC1) */
#define REG_DAC11_VOL_DAC1_ADDR 0x16
#define REG_DAC11_VOL_DAC1_BYTE 1
#define REG_DAC11_VOL_DAC1_VALUE 0x0
/* DAC12_VOL - Registers (DAC1) */
#define REG_DAC12_VOL_DAC1_ADDR 0x17
#define REG_DAC12_VOL_DAC1_BYTE 1
#define REG_DAC12_VOL_DAC1_VALUE 0x0
/* DAC13_VOL - Registers (DAC1) */
#define REG_DAC13_VOL_DAC1_ADDR 0x18
#define REG_DAC13_VOL_DAC1_BYTE 1
#define REG_DAC13_VOL_DAC1_VALUE 0x0
/* DAC14_VOL - Registers (DAC1) */
#define REG_DAC14_VOL_DAC1_ADDR 0x19
#define REG_DAC14_VOL_DAC1_BYTE 1
#define REG_DAC14_VOL_DAC1_VALUE 0x0
/* DAC15_VOL - Registers (DAC1) */
#define REG_DAC15_VOL_DAC1_ADDR 0x1A
#define REG_DAC15_VOL_DAC1_BYTE 1
#define REG_DAC15_VOL_DAC1_VALUE 0x0
/* DAC16_VOL - Registers (DAC1) */
#define REG_DAC16_VOL_DAC1_ADDR 0x1B
#define REG_DAC16_VOL_DAC1_BYTE 1
#define REG_DAC16_VOL_DAC1_VALUE 0x0
/* CM_SEL_PAD_STRGTH - Registers (DAC1) */
#define REG_CM_SEL_PAD_STRGTH_DAC1_ADDR 0x1C
#define REG_CM_SEL_PAD_STRGTH_DAC1_BYTE 1
#define REG_CM_SEL_PAD_STRGTH_DAC1_VALUE 0x20
/* DAC_POWER1 - Registers (DAC1) */
#define REG_DAC_POWER1_DAC1_ADDR 0x1D
#define REG_DAC_POWER1_DAC1_BYTE 1
#define REG_DAC_POWER1_DAC1_VALUE 0xAA
/* DAC_POWER2 - Registers (DAC1) */
#define REG_DAC_POWER2_DAC1_ADDR 0x1E
#define REG_DAC_POWER2_DAC1_BYTE 1
#define REG_DAC_POWER2_DAC1_VALUE 0xAA
/* DAC_POWER3 - Registers (DAC1) */
#define REG_DAC_POWER3_DAC1_ADDR 0x1F
#define REG_DAC_POWER3_DAC1_BYTE 1
#define REG_DAC_POWER3_DAC1_VALUE 0xAA
/* DAC_POWER4 - Registers (DAC1) */
#define REG_DAC_POWER4_DAC1_ADDR 0x20
#define REG_DAC_POWER4_DAC1_BYTE 1
#define REG_DAC_POWER4_DAC1_VALUE 0xAA
/*
*
* Control register's field descriptions
*
*/
/* PLL_CLK_CTRL0 (DAC1) */
#define R0_PUP_DAC1 0x1 /* 1b [0] */
#define R0_MCS_DAC1 0x2 /* 10b [2:1] */
#define R0_SOFT_RST_DAC1 0x0 /* 0b [3] */
#define R0_XTAL_SET_DAC1 0x0 /* 00b [5:4] */
#define R0_PLLIN_DAC1 0x0 /* 00b [7:6] */
#define R0_PUP_DAC1_MASK 0x1
#define R0_PUP_DAC1_SHIFT 0
#define R0_MCS_DAC1_MASK 0x6
#define R0_MCS_DAC1_SHIFT 1
#define R0_SOFT_RST_DAC1_MASK 0x8
#define R0_SOFT_RST_DAC1_SHIFT 3
#define R0_XTAL_SET_DAC1_MASK 0x30
#define R0_XTAL_SET_DAC1_SHIFT 4
#define R0_PLLIN_DAC1_MASK 0xC0
#define R0_PLLIN_DAC1_SHIFT 6
/* PLL_CLK_CTRL1 (DAC1) */
#define R1_CLK_SEL_DAC1 0x0 /* 0b [0] */
#define R1_VREF_EN_DAC1 0x1 /* 1b [1] */
#define R1_PLL_LOCK_DAC1 0x0 /* 0b [2] */
#define R1_PLL_MUTE_DAC1 0x1 /* 1b [3] */
#define R1_MCLKO_SEL_DAC1 0x3 /* 11b [5:4] */
#define R1_LOPWR_MODE_DAC1 0x0 /* 00b [7:6] */
#define R1_CLK_SEL_DAC1_MASK 0x1
#define R1_CLK_SEL_DAC1_SHIFT 0
#define R1_VREF_EN_DAC1_MASK 0x2
#define R1_VREF_EN_DAC1_SHIFT 1
#define R1_PLL_LOCK_DAC1_MASK 0x4
#define R1_PLL_LOCK_DAC1_SHIFT 2
#define R1_PLL_MUTE_DAC1_MASK 0x8
#define R1_PLL_MUTE_DAC1_SHIFT 3
#define R1_MCLKO_SEL_DAC1_MASK 0x30
#define R1_MCLKO_SEL_DAC1_SHIFT 4
#define R1_LOPWR_MODE_DAC1_MASK 0xC0
#define R1_LOPWR_MODE_DAC1_SHIFT 6
/* PDN_THRMSENS_CTRL_1 (DAC1) */
#define R2_VREG_PDN_DAC1 0x0 /* 0b [0] */
#define R2_PLL_PDN_DAC1 0x0 /* 0b [1] */
#define R2_TS_PDN_DAC1 0x0 /* 0b [2] */
#define R2_THRM_GO_DAC1 0x1 /* 1b [4] */
#define R2_THRM_MODE_DAC1 0x1 /* 1b [5] */
#define R2_THRM_RATE_DAC1 0x2 /* 10b [7:6] */
#define R2_VREG_PDN_DAC1_MASK 0x1
#define R2_VREG_PDN_DAC1_SHIFT 0
#define R2_PLL_PDN_DAC1_MASK 0x2
#define R2_PLL_PDN_DAC1_SHIFT 1
#define R2_TS_PDN_DAC1_MASK 0x4
#define R2_TS_PDN_DAC1_SHIFT 2
#define R2_THRM_GO_DAC1_MASK 0x10
#define R2_THRM_GO_DAC1_SHIFT 4
#define R2_THRM_MODE_DAC1_MASK 0x20
#define R2_THRM_MODE_DAC1_SHIFT 5
#define R2_THRM_RATE_DAC1_MASK 0xC0
#define R2_THRM_RATE_DAC1_SHIFT 6
/* PDN_CTRL2 (DAC1) */
#define R3_DAC01_PDN_DAC1 0x0 /* 0b [0] */
#define R3_DAC02_PDN_DAC1 0x0 /* 0b [1] */
#define R3_DAC03_PDN_DAC1 0x0 /* 0b [2] */
#define R3_DAC04_PDN_DAC1 0x0 /* 0b [3] */
#define R3_DAC05_PDN_DAC1 0x0 /* 0b [4] */
#define R3_DAC06_PDN_DAC1 0x0 /* 0b [5] */
#define R3_DAC07_PDN_DAC1 0x0 /* 0b [6] */
#define R3_DAC08_PDN_DAC1 0x0 /* 0b [7] */
#define R3_DAC01_PDN_DAC1_MASK 0x1
#define R3_DAC01_PDN_DAC1_SHIFT 0
#define R3_DAC02_PDN_DAC1_MASK 0x2
#define R3_DAC02_PDN_DAC1_SHIFT 1
#define R3_DAC03_PDN_DAC1_MASK 0x4
#define R3_DAC03_PDN_DAC1_SHIFT 2
#define R3_DAC04_PDN_DAC1_MASK 0x8
#define R3_DAC04_PDN_DAC1_SHIFT 3
#define R3_DAC05_PDN_DAC1_MASK 0x10
#define R3_DAC05_PDN_DAC1_SHIFT 4
#define R3_DAC06_PDN_DAC1_MASK 0x20
#define R3_DAC06_PDN_DAC1_SHIFT 5
#define R3_DAC07_PDN_DAC1_MASK 0x40
#define R3_DAC07_PDN_DAC1_SHIFT 6
#define R3_DAC08_PDN_DAC1_MASK 0x80
#define R3_DAC08_PDN_DAC1_SHIFT 7
/* PDN_CTRL3 (DAC1) */
#define R4_DAC09_PDN_DAC1 0x0 /* 0b [0] */
#define R4_DAC10_PDN_DAC1 0x0 /* 0b [1] */
#define R4_DAC11_PDN_DAC1 0x0 /* 0b [2] */
#define R4_DAC12_PDN_DAC1 0x0 /* 0b [3] */
#define R4_DAC13_PDN_DAC1 0x0 /* 0b [4] */
#define R4_DAC14_PDN_DAC1 0x0 /* 0b [5] */
#define R4_DAC15_PDN_DAC1 0x0 /* 0b [6] */
#define R4_DAC16_PDN_DAC1 0x0 /* 0b [7] */
#define R4_DAC09_PDN_DAC1_MASK 0x1
#define R4_DAC09_PDN_DAC1_SHIFT 0
#define R4_DAC10_PDN_DAC1_MASK 0x2
#define R4_DAC10_PDN_DAC1_SHIFT 1
#define R4_DAC11_PDN_DAC1_MASK 0x4
#define R4_DAC11_PDN_DAC1_SHIFT 2
#define R4_DAC12_PDN_DAC1_MASK 0x8
#define R4_DAC12_PDN_DAC1_SHIFT 3
#define R4_DAC13_PDN_DAC1_MASK 0x10
#define R4_DAC13_PDN_DAC1_SHIFT 4
#define R4_DAC14_PDN_DAC1_MASK 0x20
#define R4_DAC14_PDN_DAC1_SHIFT 5
#define R4_DAC15_PDN_DAC1_MASK 0x40
#define R4_DAC15_PDN_DAC1_SHIFT 6
#define R4_DAC16_PDN_DAC1_MASK 0x80
#define R4_DAC16_PDN_DAC1_SHIFT 7
/* THRM_TEMP_STAT (DAC1) */
#define R5_TEMP_DAC1 0x00 /* 00000000b [7:0] */
#define R5_TEMP_DAC1_MASK 0xFF
#define R5_TEMP_DAC1_SHIFT 0
/* DAC_CTRL0 (DAC1) */
#define R6_MMUTE_DAC1 0x0 /* 0b [0] */
#define R6_FS_DAC1 0x2 /* 10b [2:1] */
#define R6_SAI_DAC1 0x4 /* 100b [5:3] */
#define R6_SDATA_FMT_DAC1 0x1 /* 01b [7:6] */
#define R6_MMUTE_DAC1_MASK 0x1
#define R6_MMUTE_DAC1_SHIFT 0
#define R6_FS_DAC1_MASK 0x6
#define R6_FS_DAC1_SHIFT 1
#define R6_SAI_DAC1_MASK 0x38
#define R6_SAI_DAC1_SHIFT 3
#define R6_SDATA_FMT_DAC1_MASK 0xC0
#define R6_SDATA_FMT_DAC1_SHIFT 6
/* DAC_CTRL1 (DAC1) */
#define R7_SAI_MS_DAC1 0x0 /* 0b [0] */
#define R7_BCLK_EDGE_DAC1 0x0 /* 0b [1] */
#define R7_BCLK_RATE_DAC1 0x0 /* 0b [2] */
#define R7_SAI_MSB_DAC1 0x0 /* 0b [4] */
#define R7_LRCLK_POL_DAC1 0x0 /* 0b [5] */
#define R7_LRCLK_MODE_DAC1 0x0 /* 0b [6] */
#define R7_BCLK_GEN_DAC1 0x0 /* 0b [7] */
#define R7_SAI_MS_DAC1_MASK 0x1
#define R7_SAI_MS_DAC1_SHIFT 0
#define R7_BCLK_EDGE_DAC1_MASK 0x2
#define R7_BCLK_EDGE_DAC1_SHIFT 1
#define R7_BCLK_RATE_DAC1_MASK 0x4
#define R7_BCLK_RATE_DAC1_SHIFT 2
#define R7_SAI_MSB_DAC1_MASK 0x10
#define R7_SAI_MSB_DAC1_SHIFT 4
#define R7_LRCLK_POL_DAC1_MASK 0x20
#define R7_LRCLK_POL_DAC1_SHIFT 5
#define R7_LRCLK_MODE_DAC1_MASK 0x40
#define R7_LRCLK_MODE_DAC1_SHIFT 6
#define R7_BCLK_GEN_DAC1_MASK 0x80
#define R7_BCLK_GEN_DAC1_SHIFT 7
/* DAC_CTRL2 (DAC1) */
#define R8_DE_EMP_EN_DAC1 0x0 /* 0b [0] */
#define R8_DAC_OSR_DAC1 0x0 /* 0b [1] */
#define R8_AUTO_MUTE_EN_DAC1 0x1 /* 1b [2] */
#define R8_DAC_POL_DAC1 0x0 /* 0b [3] */
#define R8_BCLK_TDMC_DAC1 0x0 /* 0b [4] */
#define R8_VREG_CTRL_DAC1 0x0 /* 00b [6:5] */
#define R8_DE_EMP_EN_DAC1_MASK 0x1
#define R8_DE_EMP_EN_DAC1_SHIFT 0
#define R8_DAC_OSR_DAC1_MASK 0x2
#define R8_DAC_OSR_DAC1_SHIFT 1
#define R8_AUTO_MUTE_EN_DAC1_MASK 0x4
#define R8_AUTO_MUTE_EN_DAC1_SHIFT 2
#define R8_DAC_POL_DAC1_MASK 0x8
#define R8_DAC_POL_DAC1_SHIFT 3
#define R8_BCLK_TDMC_DAC1_MASK 0x10
#define R8_BCLK_TDMC_DAC1_SHIFT 4
#define R8_VREG_CTRL_DAC1_MASK 0x60
#define R8_VREG_CTRL_DAC1_SHIFT 5
/* DAC_MUTE1 (DAC1) */
#define R9_DAC01_MUTE_DAC1 0x0 /* 0b [0] */
#define R9_DAC02_MUTE_DAC1 0x0 /* 0b [1] */
#define R9_DAC03_MUTE_DAC1 0x0 /* 0b [2] */
#define R9_DAC04_MUTE_DAC1 0x0 /* 0b [3] */
#define R9_DAC05_MUTE_DAC1 0x0 /* 0b [4] */
#define R9_DAC06_MUTE_DAC1 0x0 /* 0b [5] */
#define R9_DAC07_MUTE_DAC1 0x0 /* 0b [6] */
#define R9_DAC08_MUTE_DAC1 0x0 /* 0b [7] */
#define R9_DAC01_MUTE_DAC1_MASK 0x1
#define R9_DAC01_MUTE_DAC1_SHIFT 0
#define R9_DAC02_MUTE_DAC1_MASK 0x2
#define R9_DAC02_MUTE_DAC1_SHIFT 1
#define R9_DAC03_MUTE_DAC1_MASK 0x4
#define R9_DAC03_MUTE_DAC1_SHIFT 2
#define R9_DAC04_MUTE_DAC1_MASK 0x8
#define R9_DAC04_MUTE_DAC1_SHIFT 3
#define R9_DAC05_MUTE_DAC1_MASK 0x10
#define R9_DAC05_MUTE_DAC1_SHIFT 4
#define R9_DAC06_MUTE_DAC1_MASK 0x20
#define R9_DAC06_MUTE_DAC1_SHIFT 5
#define R9_DAC07_MUTE_DAC1_MASK 0x40
#define R9_DAC07_MUTE_DAC1_SHIFT 6
#define R9_DAC08_MUTE_DAC1_MASK 0x80
#define R9_DAC08_MUTE_DAC1_SHIFT 7
/* DAC_MUTE2 (DAC1) */
#define R10_DAC09_MUTE_DAC1 0x0 /* 0b [0] */
#define R10_DAC10_MUTE_DAC1 0x0 /* 0b [1] */
#define R10_DAC11_MUTE_DAC1 0x0 /* 0b [2] */
#define R10_DAC12_MUTE_DAC1 0x0 /* 0b [3] */
#define R10_DAC13_MUTE_DAC1 0x0 /* 0b [4] */
#define R10_DAC14_MUTE_DAC1 0x0 /* 0b [5] */
#define R10_DAC15_MUTE_DAC1 0x0 /* 0b [6] */
#define R10_DAC16_MUTE_DAC1 0x0 /* 0b [7] */
#define R10_DAC09_MUTE_DAC1_MASK 0x1
#define R10_DAC09_MUTE_DAC1_SHIFT 0
#define R10_DAC10_MUTE_DAC1_MASK 0x2
#define R10_DAC10_MUTE_DAC1_SHIFT 1
#define R10_DAC11_MUTE_DAC1_MASK 0x4
#define R10_DAC11_MUTE_DAC1_SHIFT 2
#define R10_DAC12_MUTE_DAC1_MASK 0x8
#define R10_DAC12_MUTE_DAC1_SHIFT 3
#define R10_DAC13_MUTE_DAC1_MASK 0x10
#define R10_DAC13_MUTE_DAC1_SHIFT 4
#define R10_DAC14_MUTE_DAC1_MASK 0x20
#define R10_DAC14_MUTE_DAC1_SHIFT 5
#define R10_DAC15_MUTE_DAC1_MASK 0x40
#define R10_DAC15_MUTE_DAC1_SHIFT 6
#define R10_DAC16_MUTE_DAC1_MASK 0x80
#define R10_DAC16_MUTE_DAC1_SHIFT 7
/* DACMSTR_VOL (DAC1) */
#define R11_DACMSTR_VOL_DAC1 0x00 /* 00000000b [7:0] */
#define R11_DACMSTR_VOL_DAC1_MASK 0xFF
#define R11_DACMSTR_VOL_DAC1_SHIFT 0
/* DAC01_VOL (DAC1) */
#define R12_DAC01_VOL_DAC1 0x00 /* 00000000b [7:0] */
#define R12_DAC01_VOL_DAC1_MASK 0xFF
#define R12_DAC01_VOL_DAC1_SHIFT 0
/* DAC02_VOL (DAC1) */
#define R13_DAC02_VOL_DAC1 0x00 /* 00000000b [7:0] */
#define R13_DAC02_VOL_DAC1_MASK 0xFF
#define R13_DAC02_VOL_DAC1_SHIFT 0
/* DAC03_VOL (DAC1) */
#define R14_DAC03_VOL_DAC1 0x00 /* 00000000b [7:0] */
#define R14_DAC03_VOL_DAC1_MASK 0xFF
#define R14_DAC03_VOL_DAC1_SHIFT 0
/* DAC04_VOL (DAC1) */
#define R15_DAC04_VOL_DAC1 0x00 /* 00000000b [7:0] */
#define R15_DAC04_VOL_DAC1_MASK 0xFF
#define R15_DAC04_VOL_DAC1_SHIFT 0
/* DAC05_VOL (DAC1) */
#define R16_DAC05_VOL_DAC1 0x00 /* 00000000b [7:0] */
#define R16_DAC05_VOL_DAC1_MASK 0xFF
#define R16_DAC05_VOL_DAC1_SHIFT 0
/* DAC06_VOL (DAC1) */
#define R17_DAC06_VOL_DAC1 0x00 /* 00000000b [7:0] */
#define R17_DAC06_VOL_DAC1_MASK 0xFF
#define R17_DAC06_VOL_DAC1_SHIFT 0
/* DAC07_VOL (DAC1) */
#define R18_DAC07_VOL_DAC1 0x00 /* 00000000b [7:0] */
#define R18_DAC07_VOL_DAC1_MASK 0xFF
#define R18_DAC07_VOL_DAC1_SHIFT 0
/* DAC08_VOL (DAC1) */
#define R19_DAC08_VOL_DAC1 0x00 /* 00000000b [7:0] */
#define R19_DAC08_VOL_DAC1_MASK 0xFF
#define R19_DAC08_VOL_DAC1_SHIFT 0
/* DAC09_VOL (DAC1) */
#define R20_DAC09_VOL_DAC1 0x00 /* 00000000b [7:0] */
#define R20_DAC09_VOL_DAC1_MASK 0xFF
#define R20_DAC09_VOL_DAC1_SHIFT 0
/* DAC10_VOL (DAC1) */
#define R21_DAC10_VOL_DAC1 0x00 /* 00000000b [7:0] */
#define R21_DAC10_VOL_DAC1_MASK 0xFF
#define R21_DAC10_VOL_DAC1_SHIFT 0
/* DAC11_VOL (DAC1) */
#define R22_DAC11_VOL_DAC1 0x00 /* 00000000b [7:0] */
#define R22_DAC11_VOL_DAC1_MASK 0xFF
#define R22_DAC11_VOL_DAC1_SHIFT 0
/* DAC12_VOL (DAC1) */
#define R23_DAC12_VOL_DAC1 0x00 /* 00000000b [7:0] */
#define R23_DAC12_VOL_DAC1_MASK 0xFF
#define R23_DAC12_VOL_DAC1_SHIFT 0
/* DAC13_VOL (DAC1) */
#define R24_DAC13_VOL_DAC1 0x00 /* 00000000b [7:0] */
#define R24_DAC13_VOL_DAC1_MASK 0xFF
#define R24_DAC13_VOL_DAC1_SHIFT 0
/* DAC14_VOL (DAC1) */
#define R25_DAC14_VOL_DAC1 0x00 /* 00000000b [7:0] */
#define R25_DAC14_VOL_DAC1_MASK 0xFF
#define R25_DAC14_VOL_DAC1_SHIFT 0
/* DAC15_VOL (DAC1) */
#define R26_DAC15_VOL_DAC1 0x00 /* 00000000b [7:0] */
#define R26_DAC15_VOL_DAC1_MASK 0xFF
#define R26_DAC15_VOL_DAC1_SHIFT 0
/* DAC16_VOL (DAC1) */
#define R27_DAC16_VOL_DAC1 0x00 /* 00000000b [7:0] */
#define R27_DAC16_VOL_DAC1_MASK 0xFF
#define R27_DAC16_VOL_DAC1_SHIFT 0
/* CM_SEL_PAD_STRGTH (DAC1) */
#define R28_CM_SEL_DAC1 0x0 /* 0b [1] */
#define R28_PAD_DRV_DAC1 0x1 /* 1b [5] */
#define R28_CM_SEL_DAC1_MASK 0x2
#define R28_CM_SEL_DAC1_SHIFT 1
#define R28_PAD_DRV_DAC1_MASK 0x20
#define R28_PAD_DRV_DAC1_SHIFT 5
/* DAC_POWER1 (DAC1) */
#define R29_DAC01_POWER_DAC1 0x2 /* 10b [1:0] */
#define R29_DAC02_POWER_DAC1 0x2 /* 10b [3:2] */
#define R29_DAC03_POWER_DAC1 0x2 /* 10b [5:4] */
#define R29_DAC04_POWER_DAC1 0x2 /* 10b [7:6] */
#define R29_DAC01_POWER_DAC1_MASK 0x3
#define R29_DAC01_POWER_DAC1_SHIFT 0
#define R29_DAC02_POWER_DAC1_MASK 0xC
#define R29_DAC02_POWER_DAC1_SHIFT 2
#define R29_DAC03_POWER_DAC1_MASK 0x30
#define R29_DAC03_POWER_DAC1_SHIFT 4
#define R29_DAC04_POWER_DAC1_MASK 0xC0
#define R29_DAC04_POWER_DAC1_SHIFT 6
/* DAC_POWER2 (DAC1) */
#define R30_DAC05_POWER_DAC1 0x2 /* 10b [1:0] */
#define R30_DAC06_POWER_DAC1 0x2 /* 10b [3:2] */
#define R30_DAC07_POWER_DAC1 0x2 /* 10b [5:4] */
#define R30_DAC08_POWER_DAC1 0x2 /* 10b [7:6] */
#define R30_DAC05_POWER_DAC1_MASK 0x3
#define R30_DAC05_POWER_DAC1_SHIFT 0
#define R30_DAC06_POWER_DAC1_MASK 0xC
#define R30_DAC06_POWER_DAC1_SHIFT 2
#define R30_DAC07_POWER_DAC1_MASK 0x30
#define R30_DAC07_POWER_DAC1_SHIFT 4
#define R30_DAC08_POWER_DAC1_MASK 0xC0
#define R30_DAC08_POWER_DAC1_SHIFT 6
/* DAC_POWER3 (DAC1) */
#define R31_DAC09_POWER_DAC1 0x2 /* 10b [1:0] */
#define R31_DAC10_POWER_DAC1 0x2 /* 10b [3:2] */
#define R31_DAC11_POWER_DAC1 0x2 /* 10b [5:4] */
#define R31_DAC12_POWER_DAC1 0x2 /* 10b [7:6] */
#define R31_DAC09_POWER_DAC1_MASK 0x3
#define R31_DAC09_POWER_DAC1_SHIFT 0
#define R31_DAC10_POWER_DAC1_MASK 0xC
#define R31_DAC10_POWER_DAC1_SHIFT 2
#define R31_DAC11_POWER_DAC1_MASK 0x30
#define R31_DAC11_POWER_DAC1_SHIFT 4
#define R31_DAC12_POWER_DAC1_MASK 0xC0
#define R31_DAC12_POWER_DAC1_SHIFT 6
/* DAC_POWER4 (DAC1) */
#define R32_DAC13_POWER_DAC1 0x2 /* 10b [1:0] */
#define R32_DAC14_POWER_DAC1 0x2 /* 10b [3:2] */
#define R32_DAC15_POWER_DAC1 0x2 /* 10b [5:4] */
#define R32_DAC16_POWER_DAC1 0x2 /* 10b [7:6] */
#define R32_DAC13_POWER_DAC1_MASK 0x3
#define R32_DAC13_POWER_DAC1_SHIFT 0
#define R32_DAC14_POWER_DAC1_MASK 0xC
#define R32_DAC14_POWER_DAC1_SHIFT 2
#define R32_DAC15_POWER_DAC1_MASK 0x30
#define R32_DAC15_POWER_DAC1_SHIFT 4
#define R32_DAC16_POWER_DAC1_MASK 0xC0
#define R32_DAC16_POWER_DAC1_SHIFT 6
#endifAnd thats all the control code for the DAC.
This maps all the functions of the DSP for the MCU.
All this code was Auto-generated in about 5 Seconds and is ready to be implemented.
Pretty impressive Mr. Analog Devices !
Last edited:
Cool!
I am just getting my feet wet with Sigma Studio using an ADAU1452 EVAL board. I have a question about the above code...
So I assume that this is spit out of Sigma Studio after you compile the project? Then what - I guess it has to be loaded to the board, specifically the register setting parts of the code? Is that right? Can you give a rough outline of how the code is loaded?
Thanks!
I am just getting my feet wet with Sigma Studio using an ADAU1452 EVAL board. I have a question about the above code...
So I assume that this is spit out of Sigma Studio after you compile the project? Then what - I guess it has to be loaded to the board, specifically the register setting parts of the code? Is that right? Can you give a rough outline of how the code is loaded?
Thanks!
Last edited:
The only time you need to generate code like that is if you are planing to embed and run a standalone micro controller if your planning to use it without a computer.
In this case, this code is for the DAC ( ADAU1966 ) and is mainly for Volume control ( Master and Individual ), Mute and Drive Strength ( Can be set to either 4mA or 8mA )
PS:
V3 ( 36pin output header ) Board has shrunk to just only 110x75mm
Also added 3 larger ( 100uF 16V ) caps on-board.
In this case, this code is for the DAC ( ADAU1966 ) and is mainly for Volume control ( Master and Individual ), Mute and Drive Strength ( Can be set to either 4mA or 8mA )
PS:
V3 ( 36pin output header ) Board has shrunk to just only 110x75mm
Also added 3 larger ( 100uF 16V ) caps on-board.
Last edited:
Yes, that is the general idea. I would control the ADAU using I2C from an Arduino. I am wondering how exactly you load the file from the micro controller.
When the processor powers up it starts to upload the "code" to the attached devices.
Changes to the registers are changed as they are "modified"
As you can see the DAC settings are minimal at best, also you have to open up these files and have to do some "mods" as they aren't "addressed" from default ( see code snippet below)
Mines actually can be set, and as I mentioned earlier my DAC's are going to be 0x04 and 0x24.
I will generate Some Example code for the Trio tomorrow..
Changes to the registers are changed as they are "modified"
As you can see the DAC settings are minimal at best, also you have to open up these files and have to do some "mods" as they aren't "addressed" from default ( see code snippet below)
Code:
#define DEVICE_ADDR_DAC1 0x0Mines actually can be set, and as I mentioned earlier my DAC's are going to be 0x04 and 0x24.
I will generate Some Example code for the Trio tomorrow..
Hey guys...
Been busy poking away at the DAC board yet again.
After careful consideration a 4 layer board is needed to keep Digital "artifacts" from straying.
And here's the end product
First / Signal Layer
Second / GND Layer
Third / Output Layer
Fourth / Power Layer
Been busy poking away at the DAC board yet again.
After careful consideration a 4 layer board is needed to keep Digital "artifacts" from straying.
And here's the end product
First / Signal Layer
An externally hosted image should be here but it was not working when we last tested it.
Second / GND Layer
An externally hosted image should be here but it was not working when we last tested it.
Third / Output Layer
An externally hosted image should be here but it was not working when we last tested it.
Fourth / Power Layer
An externally hosted image should be here but it was not working when we last tested it.
- Status
- This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.