My Complete Solution DAC, RFC

[geekysuavo]

looks good. i'm still working on the dac output idea. it looks like the spikes can't be erased without using something other than pulses, so i'm focusing onto a peicewise approach that still takes rise time into account.

i think dynamically changing the output impedance depending on the step value may be a bit too difficult, for now... without knowing the exact impedances of the resistors in the ladder, how would one even go about such a thing?

~ brad.

 

[geekysuavo]

look ma, no spikes!

alright, here's progress: changing to piecewise linear functions produces much cleaner results, and it looks more accurate too, in my humble opinion...

the current problem is, the sinusoid doesn't repeat itself, so i'm hacking in a "number of periods" variable to the program so i can get, say, ten periods for analysis. after that i can look at the results when coupled to my i/v stage.

~ brad.

 

[abraxalito]

i think dynamically changing the output impedance depending on the step value may be a bit too difficult, for now... without knowing the exact impedances of the resistors in the ladder, how would one even go about such a thing?

I think the resistor value could be estimated and played around with. That's not such a big problem as not knowing the particular DAC architecture. BB/TI is rather coy about telling us what's inside the 1704 - we know there are two 23-bit DACs, but they're not completely independent ones.

The two DACs share a common reference and a common R-2R ladder for the bit current sources.

There's also the small matter of the quoted 1k typical output impedance - it seems way too low, and inverse R-2R ladder DACs (as I assume this one is) don't have a 'typical' output impedance.

 

[abraxalito]

alright, here's progress: changing to piecewise linear functions produces much cleaner results, and it looks more accurate too, in my humble opinion...

the current problem is, the sinusoid doesn't repeat itself, so i'm hacking in a "number of periods" variable to the program so i can get, say, ten periods for analysis. after that i can look at the results when coupled to my i/v stage.

I'm guessing you can set the frequency of your test waveform to a sub-multiple of the sample rate, it looks to be what TI did on their DAC testing. Otherwise why did they choose to test at 1.1kHz - that would be about 40 samples per cycle. I agree your latest plots look far more promising

 

[geekysuavo]

ok, this is very rough data, so bear with me... i'm still working out some kinks.

color codes:
pure sine wave in red,
raw dac output in green,
pass i/v stage w/o 10nF cap in blue,
pass i/v stage w/ 10nF cap in purple

the third attachment shows an fft of the output waveforms. x-axis values are not frequency values, but more like bucket indices. the second and third harmonics are slightly higher for the cap'ed version, but higher-order (4+) harmonics fall off much faster than without the 10nF cap.

i'll have some quantitative thd estimates to post within a week or so. (i'm using another c program to perform the fft, so it's a matter of programming more than anything else... )

~ brad.

 

[abraxalito]

I'd suggest caution in interpreting the FFT measurements when feeding in the quantized sinewave. That's because when we put in a repetitive signal, the quantising distortion does not get smeared out across the whole audio band, rather it becomes correlated with the signal and piles up around multiples of the input frequency. So the harmonics you've plotted may well not be harmonic distortion from your I/V converter, they'll likely be from the quantization distortion of the test waveform.

 

[geekysuavo]

... So the harmonics you've plotted may well not be harmonic distortion from your I/V converter, they'll likely be from the quantization distortion of the test waveform.

ah, that makes more sense! it's starting to look like the fft i'm using needs more work or perhaps isn't suitable to analyze output distortion. i was initially trying it to confirm the unusually high THD estimates i was getting from the spice fourier analysis.

time for more work.

~ brad.

 

[geekysuavo]

following your advice on other fets in the i/v stage, i went ahead and simulated the current design with a jfet (2sk170) device at the input. almost identical distortion figures (barely lower) and increased HF response by about half a decade. transconductance of the jfet is around the same in the circuit as that of the original mosfet. i've attached the simulation schematic. any thoughts?

~ brad.

 

[geekysuavo]

while i'm thinking about it, i've got a (probably stupid) question... would replacing the df1704 with a df1706 in 4x mode allow me to run the pcm1704's at a "192khz sample rate" (i.e. could i use the 192khz upsampling rate of the asrc?), or is that not feasible?

thanks,
~ brad.

 

[abraxalito]

i've attached the simulation schematic. any thoughts?

What models are you using for the JFET and MOSFET? Would you post them up or provide links so I can have a play in LTSpice?

Last week I spent many hours on the sim getting a step waveform to work in LTSpice. Eventually I got something that looked reasonable and fed it into a couple of opamp-based I/V converters. My fairly tentative hypothesis at this stage is that chasing after ultra-low THD figures isn't worthwhile, for a couple of reasons. One is that the models probably aren't close enough to reality to make this meaningful. A second reason is that sound quality doesn't seem to be strongly related to THD figures - we're measuring the wrong thing in my opinion. So my line of study has been non-harmonic distortion - looking for ways that the noise floor is modulated. Progress has been fairly slow, but I am seeing some differences in this area with different component values, some of the results do correlate with my sound quality impressions, but some other results show a negative correlation I'm keen to understand why people would prefer passive I/V and non-f/b to opamp.

As regards your digital filter question - its definitely not a stupid one - it looks very confusing what TI are saying about the DF1706. They say its a 'companion filter' for the PCM1704 but its performance on paper exceeds that claimed in the datasheet for the PCM1704. In particular, the PCM1704 is limited to a max bit clock of 25MHz, meaning it can only do 4fs at 192kHz. Perhaps TI are going to release a PCM1706 with a max bit clock of 50MHz which allows this filter to be used. Until then, I'd stick with the DF1704 (its a little cheaper). I've just checked on TI's website - I see they're not recommending either filter for new designs, preferring people to use their newer sigma-delta DACs. So why no such message for the PCM1704? Bizarre

 

[geekysuavo]

What models are you using for the JFET and MOSFET? Would you post them up or provide links so I can have a play in LTSpice?

the 2sk170: (bl i think)

.MODEL 2SK170 NJF(
+ VTO=-5.211e-001 BETA=3.683e-002 LAMBDA=4.829e-003
+ IS=1.000e-009, RD=0.000e+000 RS=0.000e+000
+ CGS=5.647e-011 CGD=2.562e-011
+ PB=4.860e+000 FC=0.5)

the irf610:

.SUBCKT IRF610   d  g  s 
LD d 1 5.000E-09
LS s 3 1.000E-08
RG g 2  240.    
RGS 2 3 1.000E+08
RDS 1 3 5.000E+05
M1 1 2 3 3 IRF610    L=2.0E-06 W=1.073E-02
.MODEL IRF610   NMOS (LEVEL=1 VTO= 4.000 KP=2.071E-05
+TOX=1.000E-07 UO= 600.0 LAMBDA= .001 CBD=3.087E-10
+PB= .800 MJ= .50 IS=1.000E-15 CGSO=1.165E-08 CGDO=2.330E-09
+RS=1.000E-03 RD=1.000E-03)
.ENDS IRF610

and ztx450 for the ccs bjt:

.MODEL ZTX450 NPN(IS=3.941445E-14 BF=175 VAF=109.45
+ NF=1 IKF=.8
+ ISE=7.4025E-15 NE=1.3 BR=20.5 VAR=14.25 NR=.974 IKR=.1
+ ISC=3.157E-13 NC=1.2 RB=1.1 RE=.1259 RC=.0539 CJE=63E-12
+ TF=.75E-9 CJC=15.8E-12 TR=85E-9 VJC=.505 MJC=.39)

I'm keen to understand why people would prefer passive I/V and non-f/b to opamp.

i await your results anxiously! my first guess would be that a single-ended class-a solution such as the d1 would yield lower IMD figures than any feedback design. couple it with a psu capable of transients seen in the usual programme and TIM should be low too... but i could be way off. as for the passive solutions, i'm not sure what the appeal is, especially regarding the use of transformers...

as for the decision on jfet vs mosfet at the i/v input device, i could swing either way at the moment. i'd like any opinion available...

Bizarre

quite bizarre. although it seems the df1706 is capable of operating in 4X OS mode, perhaps even as a compatibility setting for the PCM1704?

my gut instinct tells me i would prefer the sound of a true multibit dac; it's a shame (imho) that nobody's pursuing such technology anymore... a pcm1706 (which one could only surmise would be a 192khz-capable r2r dac) would be a wonderful blessing.

~ brad.

 

[geekysuavo]

ok, i'm less on the fence about the jfet input now that i've compared the two frequency responses side-by-side. the increase in hf response gained by use of the jfet is less than i first eyeballed, and gain is decreased (hence the 1.25 multiplication factor in the second plot command). i think i'll stick with the mosfet for the time being to keep close to the original d1 design.

~ brad.

 

[abraxalito]

the irf610:

That's not a particularly accurate model for doing linear simulations, in fact its fairly close to hopeless Probably its marginally ok for high drain currents, but as far as I'm aware you're running about 30mA. Its a poor model because it knows nothing about sub-threshold conduction and that's precisely the operating area in this application. After a quick google for 'sub threshold conduction' I found an article citing Fairchild's models as handling this area more accurately. On Fairchild's site, I looked for a suitable part and perhaps the FDMA410NZ might suit you - although its in a very small SMT package, it has a reasonable power dissipation. The model's sub-threshold performance looks quite respectable - it shows a gm around 600mS at 30mA with a gate voltage of 834mV.

quite bizarre. although it seems the df1706 is capable of operating in 4X OS mode, perhaps even as a compatibility setting for the PCM1704?

OK, missed that, need to go back to read the datasheet in more detail...

my gut instinct tells me i would prefer the sound of a true multibit dac; it's a shame (imho) that nobody's pursuing such technology anymore... a pcm1706 (which one could only surmise would be a 192khz-capable r2r dac) would be a wonderful blessing.

Did you take on board my earlier comments about running DACs very fast and download anything from Dan Lavry's website? There are true multibit DACs still being made, they're just not targeted at audio applications. If you really really want one, that article I linked to by Jim Williams of Linear Tech was about the LTC2757 (admittedly only 18 bits). ADI recently announced the AD5791 which is a true 20bit DAC with a 50MHz interface, so it'll do 8fs at 192kHz - bound to be expensive though!

 

[geekysuavo]

that's interesting about the sub-threshold conduction aspect of the spice models... how would i find an accurate irf610 to use in simulations? (if possible) i guess since it's a switching FET the guys at IR figured nobody cared about such a situation...

i've been cleaning up the simulation results and looking at various other FETs for use in the power supply and i/v stages... so far it looks like i'm sticking with the irf610 in the i/v stage and irfp{,9}240 in the psu...

a correction must be made to the 3.3v shunt reg comparison graph. i realized i was using irf9540's in those sims instead of irfp9240's. i've added the line rejection of the irfp9240 to the new plot as a point of comparison.

~ brad.

 

[abraxalito]

that's interesting about the sub-threshold conduction aspect of the spice models... how would i find an accurate irf610 to use in simulations? (if possible) i guess since it's a switching FET the guys at IR figured nobody cared about such a situation...

That'd be my guess too. Even in LTSpice the MOSFET models I looked at (and there are dozens, I just sampled a couple) didn't deal with this, as LTSpice's original name is SwitcherCad. That's where most MOSFETs end up I think.

a correction must be made to the 3.3v shunt reg comparison graph. i realized i was using irf9540's in those sims instead of irfp9240's. i've added the line rejection of the irfp9240 to the new plot as a point of comparison.

As you're using those switching MOSFET models I'd say those plots are now in doubt I've been thinking more generally about power supplies recently and plan to have a play (not simulate) with some chipamps as regulators to see if I can improve on the low-current performance of LM317/337s. Turns out that when feeding typical opamp type circuits those devices have appreciable output impedance.