Hi,
I tried the schematic on 2 simulators, but no matter how I try,
It doesn't work.
Don't have the models for MJ4502/802, but that is not the real problem I guess.
Dumb question: The outputs from the LM's are connected to each other. How can they drive the output transistors that way?
I'm I missing something here?
/Hugo - rather posts then have headache
I tried the schematic on 2 simulators, but no matter how I try,
It doesn't work.
Don't have the models for MJ4502/802, but that is not the real problem I guess.
Dumb question: The outputs from the LM's are connected to each other. How can they drive the output transistors that way?
I'm I missing something here?
/Hugo - rather posts then have headache
Attachments
Does the simulation model represent the op amps as "ideal" and so the model does not pick up the variations in current draw at the V+ and V- terminals that provides the variation to the transistors? Just a guess as my electrical engineering training predates simulation programs (although I could probably whip up one in FORTRAN with some punch cards!
)
-PaulyG - from the really old school...
)-PaulyG - from the really old school...
PaulyG said:
Don't know, maybe this helps:
To me this is "Latin".
.SUBCKT LM741 1 2 99 50 28
*Features:
*Improved performance over industry standards
*Plug-in replacement for LM709,LM201,MC1439,748
*Input and output overload protection
****************INPUT STAGE**************
IOS 2 1 20N
*^Input offset current
R1 1 3 250K
R2 3 2 250K
I1 4 50 100U
R3 5 99 517
R4 6 99 517
Q1 5 2 4 QX
Q2 6 7 4 QX
*Fp2=2.55 MHz
C4 5 6 60.3614P
***********COMMON MODE EFFECT***********
I2 99 50 1.6MA
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 1E-3 1
*Input offset voltage.^
R8 99 49 40K
R9 49 50 40K
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 1.63
D1 9 8 DX
D2 10 9 DX
V3 10 50 1.63
**************SECOND STAGE**************
EH 99 98 99 49 1
G1 98 9 5 6 2.1E-3
*Fp1=5 Hz
R5 98 9 95.493MEG
C3 98 9 333.33P
***************POLE STAGE***************
*Fp=30 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 5.3052E-15
*********COMMON-MODE ZERO STAGE*********
*Fpcm=300 Hz
G4 98 16 3 49 3.1623E-8
L2 98 17 530.5M
R13 17 16 1K
**************OUTPUT STAGE**************
F6 50 99 POLY(1) V6 450U 1
E1 99 23 99 15 1
R16 24 23 25
D5 26 24 DX
V6 26 22 0.65V
R17 23 25 25
D6 25 27 DX
V7 22 27 0.65V
V5 22 21 0.18V
D4 21 15 DX
V4 20 22 0.18V
D3 15 20 DX
L3 22 28 100P
RL3 22 28 100K
***************MODELS USED**************
.MODEL DX D(IS=1E-15)
.MODEL QX NPN(BF=625)
.ENDS
/Hugo - Never went to school to debug this stuff
super stuff
Netlist,
I had a similar case where the signal source was internally always connected to gound, so you couln't use it floating. This was with the Proteus simulator, don't know in your case. What if you try with one input grounded and the other one driven by a grounded signal source?
Jan Didden
Edit: Do you get an error message "..singular node..."?
Netlist,
I had a similar case where the signal source was internally always connected to gound, so you couln't use it floating. This was with the Proteus simulator, don't know in your case. What if you try with one input grounded and the other one driven by a grounded signal source?
Jan Didden
Edit: Do you get an error message "..singular node..."?
Both OPs are inverting, so if there is a positive signal on one and a negative signal on the other input, in one OP the upper output transistor will have more current and in the other the lower output transistor.
So for example, the current can flow from upper left to lower right via the 220ohm.
The that will confuse the four current sources (are the big transistors current sources ? ha ha ha) and modulate the base voltages of the big transistors, so they will do the same thing as in the OP. Current will flow from one upper side to the other lower side.
But the 741 has a crappy classB output stage IMHO.
And what do you think of my design ? Isnt it less complicated = more simple ?
So for example, the current can flow from upper left to lower right via the 220ohm.
The that will confuse the four current sources (are the big transistors current sources ? ha ha ha) and modulate the base voltages of the big transistors, so they will do the same thing as in the OP. Current will flow from one upper side to the other lower side.
But the 741 has a crappy classB output stage IMHO.
And what do you think of my design ? Isnt it less complicated = more simple ?
My calculation may be wrong, but I believe if there was no feedback, when there are +2 V and -2 V on the OPs output, 0,6 A will flow through the speaker.
0,6 A if it is a 4 ohm speaker and 0,6A if it is a 8ohm speaker.
I am afraid, this will not work, it would mean more power on 8 ohm less power on 4 ohm.
Somethings wrong...
Bernhard,
Had no time to look at your project, but I think you will get reply.
Here's what I did in the meantime.
I changed the LM741 with the current feedback OpAmp's LM6181.
Couldn't get it to work with LM741, but jh6you surely will
Added 2 100ohm resistors at the output as Nelson said.
(hope this is correct)
The only way (to me) to get rid of crossover distorsion was replacing R18 and R17 with 10k.
Now I have a nice sinewave at the outputs, 22.4V peak/peak at 8ohm before clipping.
At 4ohm I only have 7V P/P before clip.
Don't know if this is ok?
Power dissipation of transistors is 15Watt each at 8ohm and 17W at 4ohm.
/Hugo - Makes Zip-files now; is good for Jason's bandwith
Had no time to look at your project, but I think you will get reply.
Here's what I did in the meantime.
I changed the LM741 with the current feedback OpAmp's LM6181.
Couldn't get it to work with LM741, but jh6you surely will
Added 2 100ohm resistors at the output as Nelson said.
(hope this is correct)
The only way (to me) to get rid of crossover distorsion was replacing R18 and R17 with 10k.
Now I have a nice sinewave at the outputs, 22.4V peak/peak at 8ohm before clipping.
At 4ohm I only have 7V P/P before clip.
Don't know if this is ok?
Power dissipation of transistors is 15Watt each at 8ohm and 17W at 4ohm.
/Hugo - Makes Zip-files now; is good for Jason's bandwith
Getting back to Rookies post #53
The concept of the gainclone killer is interesting. Reviewing the datasheets for the OPA549, it is clear that in this config it will pass absurd amounts of current for monolithic chip amp - 15amps is very safe. The limiting factor seems to be the voltage swing possible for this chip - I get roughly 30v.
Is this analysis correct? If so, it seems that low impedence loads are desirable, thus making this a great slamming sub-amp. Total idiot?
(just bumping this concept back into the thinking of the smart thinkers in the group
)
The concept of the gainclone killer is interesting. Reviewing the datasheets for the OPA549, it is clear that in this config it will pass absurd amounts of current for monolithic chip amp - 15amps is very safe. The limiting factor seems to be the voltage swing possible for this chip - I get roughly 30v.
Is this analysis correct? If so, it seems that low impedence loads are desirable, thus making this a great slamming sub-amp. Total idiot?
(just bumping this concept back into the thinking of the smart thinkers in the group
)
jh6you said:
Looks very good, any trimming should be possible now.
Ok, I changed the transistors to MJE15030/31.
The response is as good as the MJ4502/802 but I can't get my hands on the MJ4502.
With the MJ15024/25 I couldn't tame the DC at the outputs.
Changed source resistors to 0.69 and 0.47ohm. This gives the lowest possible DC at the outputs.
Again I zipped the nodes, witch you need to understand the graphs, the DC voltage, current and powers.
In the graphs you see square and sine waves. Node numbers are below the graphs.
The square wave shows some overshoot.
Like Nelson says: Enjoy!
This is about the limit of my knowledge for the moment, let me know if this makes sense or not.
/Hugo - didn't use Halo's favourite transistors
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