You will also get it soon
PCM5101 or PCM5102 with additional LPF-Buffer (OPA1662 or equal).
No, at 1st - analog output it not the main Generator function, 2nd - this will increase the price.
If somebody wants better analog source, he can use external DAC with I2S Input.
looking at your storefront, its a lot of options and I'm confused which kit I should buy.
I would like a kit of all the parts (I don't want to chase down even a single part via mouser/etc if I don't have to), all the boards, NO BOX (I'll supply my own). I'm happy to do all the soldering that is humanly possible, that can be done by hand.
given all that (lol), which kit do I want?
thanks
I would like a kit of all the parts (I don't want to chase down even a single part via mouser/etc if I don't have to), all the boards, NO BOX (I'll supply my own). I'm happy to do all the soldering that is humanly possible, that can be done by hand.
given all that (lol), which kit do I want?
thanks
AES, costs
Hi there: Nice unit, costs seem a bit high.
Have you compared to the Neutrik or Prism spec?
Suggestions: A simple addition: a well designed AES/EBU and AES3id output, that is a 2..7V P-P bal on XLR male 110 Ohm bal, and 1.2 P-P unbal on floating BNC 75 Ohm for broadcast, studio and professional use.
Another useful improvement: Add an external house clock 10 MHz Sine eg from TCXO or GPS or Rb for precise sync and lowest jitter.
Enjoy!
Jon
Hi there: Nice unit, costs seem a bit high.
Have you compared to the Neutrik or Prism spec?
Suggestions: A simple addition: a well designed AES/EBU and AES3id output, that is a 2..7V P-P bal on XLR male 110 Ohm bal, and 1.2 P-P unbal on floating BNC 75 Ohm for broadcast, studio and professional use.
Another useful improvement: Add an external house clock 10 MHz Sine eg from TCXO or GPS or Rb for precise sync and lowest jitter.
Enjoy!
Jon
variable output on the spdif could be useful and interesting. some spdif inputs can take more or less than the 'standard' .5v signal. it would be useful to be able to test a dac or spdif-in device by sending its digital stream above and below the normal level, to see what its acceptance input range is, or even if it freaks out if you send in too much signal. if there are trafos on the next stage, having a varying digital out from your device could help identify when the trafos are saturating, for example.
An AES ouput would be useful but not necessary.
The external clock option described would not help since the jitter would be from the internal PLL, not the external source. It does support an external clock. You can connect it through the I2S input. On my to-do list is an interface so i can drive with an external modulated generator to see the jitter impact on various devices. At present I see no jitter effects on the testing I have done so far.
This is way cheaper than either the Prism or the NTI box. Neither of those have the test signal depth this provides. I hope to test the DSD and some of the other waveforms soon.
You can buy DIY Kit-2 - it includes all IC and some critical components (like TOSLINK Transmitter and SPDIF transformer).
Before this, you can download BOM and to see which other components you have, which not and to tell me. Maybe I can help you but you should understand that I'm not able to supply resistors and capacitors - to complete the kit it will takes a lot of time.
If I can, anybody can.
given all that (lol), which kit do I want?
thanks
Only you can decide
But I should mention that I stop to sale the first kit (assembled PCB), only Ki1, Kit-2 and complete device.
Price is high due to a small quantity.
for example - just for a case I pay about $90, because of a small batch ordering).
too bad you no longer have assembled board sets. to save time for me, that would have been the next best choice to a full parts kit. and full parts kits are a lot of extra effort unless you do a lot of them.
if you do decide to let a set of boards go, PM me and I'll try to do them justice in a nice DIY chassis
if you do decide to let a set of boards go, PM me and I'll try to do them justice in a nice DIY chassis
I think about this, but for the additional output connector I should increase the case, to have more space at the front panel.
I should explain a little bit a topology.
Yes, there is PLL inside, this PLL get MCLK from the Clock Oscillator, internal or external.
So, WCLK BCLK and SDATA are generated from PLL's output, but MCLK used directly fro, Oscillator.
Most of the modern DS DACs are sensitive for MCLK's jitter only, other signal's jitter is not important.
Old multibit DAC chips usually do not use MCLK but are sensitive to WCLK's jitter.
One of the future improvement which I think will be useful, is to put D-trigger (74LV1G79) before the outut buffer (it is 74LV125), so to make re-clock to WCLK.
I don't know, if it need to re-clock also BCLK and SDATA, it might be a problem at Fs=352/384kHz, where Fbclk=Fmclk with the existing 512Fs Oscillator.
Hello a precise block diagram would make you intentions clear. Reason for ext 10 MHz ref is to provice a GPS locked precice frequency. Depending on the type of PLL structure in you reclocking and the PLL jitter filter characteristics, the ref clock jitter may have impact on final clocks.
Exactly which Digital Audio Transformer shall you use in the design?
With Kind Regards,
Jon
Exactly which Digital Audio Transformer shall you use in the design?
With Kind Regards,
Jon
"Femtoclock" might be measured directly by another 24MHzclock with some slight frequency difference between them to fall between 20-20kHz.
So their actual carrier frequency for "femtoclock" is 24MHz.
By some sort of following setup:
OSC_DUT>>-Double balanced mixer>low noise amplifier + low-pass >> soundcard
OSC_REF>>/
Like this (with extra amp on the output): http://s3t.it/data/uploads/ssa_setup1.jpg
Yours, is measurement of heavily down-divided JK's clock with much lower carrier, in very different manner. You have to add 6dB for every frequency division...
15fS for 1kHz carrier... is a lot when recalculated for 24MHz.
Last edited:
There is a full schematic at the web site, "Downloads" page.
Pulse H1101NL. It works fine at 44.1 also at 192.
I'd also like to put in a vote for a 10mhz 'lab clock' external input.
its becoming common to find 10mhz sines distributed around labs (even home labs) and gear dividing it down to its internal clock freq. I have freq counters and funct gens that take 10mhz inputs (switch selectable for ext/int clocking) and it might be nice if this bit of test gear can also accept a 10mhz ref clock from external source.
that has the advantage that you can vary your external clock to simulate other test conditions, if you wish.
its becoming common to find 10mhz sines distributed around labs (even home labs) and gear dividing it down to its internal clock freq. I have freq counters and funct gens that take 10mhz inputs (switch selectable for ext/int clocking) and it might be nice if this bit of test gear can also accept a 10mhz ref clock from external source.
that has the advantage that you can vary your external clock to simulate other test conditions, if you wish.
means better mutual inductance thus better BW thus lower jitter. It has CM choke too, which is great and fixes the issues brought by P-S capacitance...
H1101NL - for a price? no brainer!
Specced for 1dB IR @ 100kHz-100MHz.
Last edited:
Yes, but have common mode filter. (Also I use symmetric circuit at the primary).
According to my experience, LAN transformers works as SPDIF much better then "special audio".
OK.
Last edited:
The measurement I compared to was done the same way as my plot, or as close as I could. I have no confidence in either. The different window functions etc. make meaningful measurements really difficult.
I know all about using double balanced mixers to zerobeat the DUT against a reference and do the phase sensitivity calculations. If I had access to their "Femtoclock" I would have done the detailed measurement. I'm not about to buy one to see how it actually measures.
I see you have attenuators on both inputs of the DBM in the picture. My understanding is that you want to drive the DBM into saturation:
(http://www.minicircuits.com/app/AN41-001.pdf)
Q. Data sheets of phase detectors indicate that both input signals, RF and LO (or RF1
and RF2) should be equal in amplitude. What happens if they are not?
A. If the signal inputs to the LO and RF ports are of sufficient magnitude, the phase
detector will operate in a saturated mode and provide a DC output proportional to the
phase difference between the two signals. However, if the LO signal is of sufficient
amplitude but the RF signal is low in amplitude, the output of the phase detector will be
proportional to the amplitude as well as the phase of the RF input. To operate the DBM
in the required saturated mode, the RF signal level should be at least:
+1 dBm for Standard Level (+7 dBm LO) mixers
+10 dBm for High Level (+17 dBm LO) mixers
+15 dBm for Very High Level (+23 dBm LO) mixers.
I know all about using double balanced mixers to zerobeat the DUT against a reference and do the phase sensitivity calculations. If I had access to their "Femtoclock" I would have done the detailed measurement. I'm not about to buy one to see how it actually measures.
I see you have attenuators on both inputs of the DBM in the picture. My understanding is that you want to drive the DBM into saturation:
(http://www.minicircuits.com/app/AN41-001.pdf)
Q. Data sheets of phase detectors indicate that both input signals, RF and LO (or RF1
and RF2) should be equal in amplitude. What happens if they are not?
A. If the signal inputs to the LO and RF ports are of sufficient magnitude, the phase
detector will operate in a saturated mode and provide a DC output proportional to the
phase difference between the two signals. However, if the LO signal is of sufficient
amplitude but the RF signal is low in amplitude, the output of the phase detector will be
proportional to the amplitude as well as the phase of the RF input. To operate the DBM
in the required saturated mode, the RF signal level should be at least:
+1 dBm for Standard Level (+7 dBm LO) mixers
+10 dBm for High Level (+17 dBm LO) mixers
+15 dBm for Very High Level (+23 dBm LO) mixers.
Jon Paul's transformers are very good and the isolation may be more important than absolute signal fidelity. They are more expensive.
I don't see a value in getting absolute accuracy in the master clock, especially using a 10 MHz oscillator as a reference. All the clocks are binary divisions of the master clock and can be created free of any artifacts except those of the master clock. The phase noise of the word clock is divined by the ratio so its really very low.
To lock it to a 10 MHz clock you need a fractional PLL of 10:49.152 Or 10:45.1584 These are not simple ratios so the PLL is more complex. Many shortcuts give you close in spurs that defeat the whole goal of low phase noise. This is also an issue in RB standards, since they have the same complex ratio issue.
In practice (see the measurements above) the jitter of this source is not significant and absolute frequency accuracy is quite good 24.575912 MHz and 22.579117 MHz whic should pose no problems for checking any digital audio device. The AES standard is +/- 100 ppm. These are well within that requirement. Remember the function of this is to test digital interfaces, not to listen to it. Its tunes are really boring. . .
I don't see a value in getting absolute accuracy in the master clock, especially using a 10 MHz oscillator as a reference. All the clocks are binary divisions of the master clock and can be created free of any artifacts except those of the master clock. The phase noise of the word clock is divined by the ratio so its really very low.
To lock it to a 10 MHz clock you need a fractional PLL of 10:49.152 Or 10:45.1584 These are not simple ratios so the PLL is more complex. Many shortcuts give you close in spurs that defeat the whole goal of low phase noise. This is also an issue in RB standards, since they have the same complex ratio issue.
In practice (see the measurements above) the jitter of this source is not significant and absolute frequency accuracy is quite good 24.575912 MHz and 22.579117 MHz whic should pose no problems for checking any digital audio device. The AES standard is +/- 100 ppm. These are well within that requirement. Remember the function of this is to test digital interfaces, not to listen to it. Its tunes are really boring. . .
The femto's measurements look like mixered for me, as the chart is a mock-up of several different measurements, in photoshop. You can see different frequency grids in the background, leftovers of these. It means the "carrier" they've measured was on different frequencies prior to photoshopping, this shouldn't happen if they used DAC's output at particular frequency (say 1kHz).
Your measurement shows much lower jitter than their's - it supports the "mixer" guess, as mixered measurement shows spurs without clock division, whereas modulated DAC output shows carrier downdivided to Fs (or Fs*OS, or many things in between given different jitter suspecabiity of different DAC structures).
As of the jitter rig... I'm currently figuring out how to make it properly, thanks for the PDF.
I'm measuring way far from DC, as everything in my setup is AC coupled, and, i try to avoid 1/f noise present everywhere in the setup. So i "measure" (ADC) between 100Hz and 10kHz of downconverted signal to get more-or-less reliable result. If the xtals are 200Hz apart in frequency, i get a downconverted carrier at 200Hz.
When i do so, i get very same charts the msbtech posted, hence my guess on their setup.
I'm working on supplementary program to do much longer FFTs (8M points) and show their SSB a-la regular signal source analyzers (at decade offsets, in dBc). So far the thing looks promising, as i'm able to see all the things i've heard about jitter, with my eyes, and somehow quantize 'em in dBc, for now - for comparisonal purposes.
Oh, the OT thing
Don't you need some sort of PLL to keep the two oscillators in quadrature (or, depending on the phase detector, in phase)? At least I don't recall having seen a phase noise measurement setup without.
Samuel
- Status
- This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.