Hi Rick,
Well what you have to do is pack up your 725 and send it me....
Okay seriously.
I removed the Jfet feedback cap altogether and bypassed to the 2k resistor then trimmed
the amplitude adjust and distortion trim.
Yes I tried subtraction/summing idea and it did not work in this oscillator.
The disto was worse no matter how much trimming I did.
This oscillator keeps getting simpler and consequently it works better.
I'm still with the added wafer and more trims idea.
This will get you what you see and -110dB re-trimming at 10KHz unless this is all an effect of harmonic cancellation.
I blew up the original fet a couple of years ago and replaced it with the same from electronic Gmine.
It's not the HP selected fet.
Cheers,
339a oscillator
Rick you do realize this is with an LT1468 for the oscillator and LME49710 metal can for the buffer.
The capacitors C32, C47, C48, C45, C46, C16, C17,C14, C15 removed. C49 changed to 0.1u polypropylene. All trims and level control pot replaced.
The quad op amp IC is a TL074 and get rid of the rest of the dangling parts.
Cheers,
Rick you do realize this is with an LT1468 for the oscillator and LME49710 metal can for the buffer.
The capacitors C32, C47, C48, C45, C46, C16, C17,C14, C15 removed. C49 changed to 0.1u polypropylene. All trims and level control pot replaced.
The quad op amp IC is a TL074 and get rid of the rest of the dangling parts.
Cheers,
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What's good for 1KHz is no good for anything else. Although for the most part everything stays under -120dB.
There has to be a better way.
What is the gate bias at different frequencies? What part did you use? We may be able to find a better alternative. I would think that the lowest resistance will add the least distortion since the series resistor will attenuate the distortion contribution of the fet. I may have this backwards.
I have been thinking about the KH feedback around the FET trick. Perhaps there is a way to sense the distortion on the fet and compare it to the mostly undistorted main wave and feedback the non-linearity to "correct" it? I would think the distortion across the FET will be higher than the main signal and some sort of comparison can be made and a correction fed into the gate. What KH is doing I think is driving the FET gate to exactly 1/2 of whatever the overall signal is. Perhaps this will linearize the fet?
On Victor's oscillator I think the 2nd was around -120 but it may have been more like -130. I can't find my notes.
Hi Demian,
It's the same part. I bought 12 of them from Electronic Goldmine a couple of years ago.
Hp used selected VCR2N. I used the generic.
Bruce Hofer used a trick of routing the distorted fet signal back to the output of an SVO and summing the two signal together to cancel part of the fet generated part of the distortion. I don't know how I would apply this here.
If it wasn't for the Jfet and AGC, I don't think I could measure any distortion at all. At least not with what I have. If I can tweak it at 1KHz where just about everything is in the noise floor.... There has got to be a way.
Maybe I should try my novel multiplier. I was saving it for my SVO design and I wasn't going let it out of the bag until then. But maybe.
At 1KHz the gate voltage is -0.511Vdc. This is the optimal where there is barely any distortion. At 10KHz the gate voltage is -1.6Vdc. If I re-trim for best distortion the gate voltage is -0.624Vdc. The Jfet exhibits the least distortion when operated near its on resistance. This makes sense since the voltage across the fet is minimal. Sound familiar?
If we could hold the voltage across the fet constant there would be no distortion at all.
Cascading does this but we'd have to use another jfet and then we are right back where we started.
Cheers,
David.
The lowest distortion is when the gate voltage approaches 0 and the channel R is lowest, but of course that isn't necessarily the best operating point for best general stability over temp, frequency, and other variables. And there is the issue of the correct drain voltage range set by the series and parallel resistors -- this is a tricky mix for sure. I've tried to keep the total resistance range, including the FET Rds range, to a factor of 2 or 3:1.
If David's approach to switching the oscillator gain trim for each range works well, then that might be able to be limited more, with a tighter range of Vds and gate voltage. This seems promising.
If David's approach to switching the oscillator gain trim for each range works well, then that might be able to be limited more, with a tighter range of Vds and gate voltage. This seems promising.
Unfortunately yes you do need some form agc. A lamp at least.
Without it all you'd be doing is setting the level. You wouldn't have time to take your measurement.
The problem lays in the linearization of the channel length modulation.
As we have seen the Jfet works best operated near it lowest R. The AC voltage across the fet is minimal and length modulation is less significant. The fet need to operate bipolar so the ususal techniques of cascading with other transistors is limited to another fet which has the same problem of the channel modulation. The trick is to make the fets involvement minimal.
Another way of controlling the loop gain is with negative resistance but then you still need a control element to vary the gain. That control element could be a variable capacitor.
Hi Dick,
The relative adjust control is on the dc side of the meter circuit.
It works in level mode only. But I see no reason why the pot itself couldn't be used for this purpose. But of course we would loose this function from the level mode.
You would still need to make up for the 10dB of gain it provides at input voltages below 1Vrms.This is all the auto set level does. The other question is will it really make that much difference. Bypass it and put 1Vrms into the analyzer and see if there is a significant difference. I don't think there is. Past the notch filter output is the 80dB of gain so what matters is the noise at that point. If you look back in the thread I calculated this for Dimitri and the answer is the residual of the 339a exactly. So it is the input circuitry and the notch filter that are responsible for the initial noise which from there is just amplified.
Cheers,
Yes, I meant re-purpose the pot. But I thought I remembered in one of your posts, David, that the auto-set level amp caused noise and distortion problems at the low end of the range when it's making up lots of gain -- was that just due to overall noise increase, and not an increase in distortion? I'm clearly confused here.
H2 is a symmretic nonlinearity so adding two won't undo it. Think of it as a big voltage coefficient on the resistance. The feedback (two resistors providing a reduced signal to the gate) reduces the nonlinearity to a first order.
If you are willing to trade settling time and absolute voltage stability you can make the resistor in series (200 Ohms I think) larger and use a lower RDS on fet. J110 or even a J108 comes to mind. It would require some careful balancing of the level adjust control and you would tweak it to operate near the on resistance across the band.
The Amber 3501 oscillator has a second harmonic cancellation trick you can try. I think I posted it earlier but I could again. It works with state variable oscillators by taking a phae shifted signal and adding some back in the right place.
Hi Dick,
No doubt the auto set level contributes noise. I made a mistake and as it turns out the noise dropped because the gain was about -5dB low. Once I balanced things up there was no savings. I thought I mentioned that in a later post.
If you take the noise measurement off the notch filter output with the QA400 or off the EMU 0204 and calculate the 80dB gain and work out the percentages it's the residual HP quotes for the analyzer.
The op amps are all low noise and I don't think they are contribute much. I think it's the amplified passives noise. The input amplifier and buffer before the notch filter are running t unity with these measurements. If I step down 20dB on the oscillator and up 20 on the analyzer input range the noise rises by that mount. The input amplifier is adding 20dB of gain at a range setting of -20dB. There is noise from the error detection circuits but if you put your scope on the output of the integrators the outputs are surprisingly quiet.
I tried bypassing the buffer stage but I'm at the noise floor of the QA400 so I can't say for sure if the noise dropped. The distortion when up so I re connected the buffer.
I'm not sure I have a great deal of trust with the QA400 as far as distortion is concerned.
I measured Victor's oscillator and got a distortion about 12 dB higher than what was measured on an AP and it doesn't compare to what others have reported on this thread. I'm going to try again using battery power because the disto may have been high from interaction of my power supply, the QA400 and the 339a. I should also try it directly with a Twin T. I haven't got to measuring the noise with the 7a22 but I will get to this. I've been focused more on getting the distortion down.
I guess what I getting at is, take care of the input noise and noise in the notch filter then the rest doesn't matter. If I disconnect the output of the notch filter from the rest of the analyzer the meter goes to zero.
Do we really need an input impedance of 100K? The input attenuator does not keep a constant load on the input amplifier's input. The overload protection diodes are suspicious. The dual gate fet is a big question mark. If we add gain at the input amplifier we improve the SNR at the cost of 3 times the distortion. But again I don't trust the QA400 at higher signal levels.
I'm still wondering about the huge amount of second harmonic on the TP for the dual gate fet in the input protection. It's coupled through some 390pF or thee about.
Cheers,
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