I scaled the visible graph from -65dBr to -160dBr to expand the area of interest, the input level is referenced as 0dBr, notched to about -35dBr, but this is not relevant.
I don't understand why people show a graph from 0dBr to say -160dBr with no information on the graph above say -100dB (except the fundamental at 0dB).... I like to zoom into the relevant area of interest on the FFT plot.
Your looking at a ''Clipped graph' the Fundamental is in fact at 0dB (notched to -35dB or so).
On the UPD the procedure is a little clumsy, I first have to turn off the notch - then set (store) the 0dB Reference, then turn the notch back on once again.
The "Store" function on the UPD sets the current signal input level as 0dBr
I don't understand why people show a graph from 0dBr to say -160dBr with no information on the graph above say -100dB (except the fundamental at 0dB).... I like to zoom into the relevant area of interest on the FFT plot.
Your looking at a ''Clipped graph' the Fundamental is in fact at 0dB (notched to -35dB or so).
On the UPD the procedure is a little clumsy, I first have to turn off the notch - then set (store) the 0dB Reference, then turn the notch back on once again.
The "Store" function on the UPD sets the current signal input level as 0dBr
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I recently brought a Krohn Hite 4402B but its really spectrally noisy, worst then my UPD:-
This -130dB limit is why I'm interested in your Sig Gen
I modified the KH-4002B with added adjustments and opamp changes.
Up to 10KHz the THD is now -130dB ... might be better, I'd have to go to the AP or ShibaSoku to see how much lower.
If you need/want better, there are only Victors' osc, (single freq) Davada's design or S.Groner's for DIY'ers.
THx-RNMarsh
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The UPD is a very old design it was released in the days when the AP1 was king of the roost - it totally decimates the AP1 and even the Sys2722. Its primary weakness is lack of native HiRes digital SPDIF I/O (its limited to a max of 50KHz) but it can generate upto 768KHz serial Data stream digitally so I designed a small dongle PCB with an FPGA to enable HiRes Digital SPDIF outputs.
While its performance is excellent, its nothing special when you consider any decent ADC with a 35dB tracking notch filter on its front end will achieve the same if not better results.
The UPD uses a Crystal CS5331 (or some such) 28pin DIL ADC - I had to the improve the decoupling around the ADC on its PSU and VRef pins to remove a whole cluster of Spurie components on the FFT noise floor.
R&S could not have sold many of these as I own 4 units between my labs here in Europe and Asia and I once met the head of there audio unit a few years ago and he commented I must own the world supply of these units...
There are a couple on Ebay I've been keeping my eye on but they lack the Digital I/O option so rather limiting - and I really need something better.
I have a scanned Ecopy of the service manual but it lacks schematics
The TI Class D modulator is challenged by its limited PWM resolution - you can see the poles in its NS design - hence the rather 'odd ball' profile of its noise floor.
The outputs of the TAS5015 where relatched to the Master clock externally to reduce the Phase noise of its PWM outputs - and this "Reference" PWM stream was feed into an Error correction output stage of my own design, basically at the time the resolution of the PWM reference was the systems limiting factor.
About 10 to 15 years ago I posted quite heavily here on DIYaudio under a thread of "Pure Digital amplifier" or some such, with many more results of different ClassD Modulator designs etc.
Heres the ESS9018 DAC at 0dB, note the flatter noise floor but a spread of THD components due to the voltage coeff and other small errors of its internal DAC array:-
https://dl.dropboxusercontent.com/u/86116171/M2SE3DB2.jpg
At -60dB the ESS9018 is THD free, note the lower noise floor which indicates the UPD dynamic range is rather stretched with a 0dB full amplitude signal:-
https://dl.dropboxusercontent.com/u/86116171/MDAC260D.jpg
I'll see if I can recover some of my files from a backup HDD, but there was a Korean company called neofidilaty (or some such) and they had a rather excellent ClassD PWM modulator design IIRC the NS6000 that had a totally flat inband noise floor while its THD was determined by external circuit design.
My expertise is in the "analogue" side of the Digital world - so dealing with Clocks, Low phase noise data relatching, Error corrected ClassD output stages etc. I moved on from pure Digital amplifiers (Digital PWM Modulators) because back in the day they where rather limited and ultimately limited the performance of my designs, I guess I just got bored and went onto other things
Today, with a decent FPGA based design its should be possible to remove this limitation, but such a FPGA based modulator is sadly beyond my skills - I'm happy working on the "Analogue" side of the Digital world
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With my KH I measured a relatively high noise floor - I'm just as interested (if not more) in the non harmonic spuire of ADC and ClassD designs so Noise floor between harmonics is more important then harmonic components (although it would be great to have a THD lower then -130dB) - I'm hoping Sams design will be spectrally cleaner then my UPD Analogue Sig gen....
such small amounts of Harmonic distortion not going to upset anyone, but Non harmonics are a different matter - indicative of potential problems under more dynamic conditions.Maybe lower noise opamps in the KH would reduce its noise floor? Do you have any FFT plots of your modified unit?
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i did the numbers and mods and pictures a year or two ago here ---- but the noise floor is a little better than stock... thd+ N = around -105 to -110dB. What number would you be happy with?
THD and THD+N:
-RNMarsh
I was pretty successful in improving the 4400, which is very similar to the 4402 with opamp swaps etc. I think I documented my efforts somewhere. If you need I can try to find my notes. It involved some bypassing of the bipolar followers and opamp swaps.
For a really clean source I got three oscillators from Vicnic http://www.diyaudio.com/forums/equi...n-audio-range-oscillator-415.html#post4380256 and run them from batteries in a metal can. Its by far the cleanest with the least spurious outputs. I persuaded him to build them at 997 Hz, 11.025 KHz and 12 KHz since those are all useful for digital testing. They are quite linear and really a value at his price. I'm sure Samuel's will be lower distortion however 2000 parts is about 10X my patience level for assembly.
For a really clean source I got three oscillators from Vicnic http://www.diyaudio.com/forums/equi...n-audio-range-oscillator-415.html#post4380256 and run them from batteries in a metal can. Its by far the cleanest with the least spurious outputs. I persuaded him to build them at 997 Hz, 11.025 KHz and 12 KHz since those are all useful for digital testing. They are quite linear and really a value at his price. I'm sure Samuel's will be lower distortion however 2000 parts is about 10X my patience level for assembly.
I see; as there is some black above -65 dB in the screenshot (in the original meaning of the word!) it first looked to me as if the scale would actually go higher, but not the plot.
Well, I presume it has a high-Z input ahead of the notch filter? That requires some quite good engineering at the -140 dB distortion level, unless they compromised noise. What's the typical THD+N figure (22 kHz), and how does THD hold up at 20 kHz?
I know I'm boring, but it is good to keep in mind that such a plot alone doesn't proof much about the distortion contribution of the analyzer. It could very well be that source and analyzer contributions cancel. To verify a -145 dB distortion level would require a source of, say, -155 dB guaranteed distortion level, which is hard to find.
Samuel
I've never looked closely at the saved files as I know what the test conditions are, but there is a Black frame around the boarder of the output plots that could appear to break the fundamental I guess....
I'm a little lost here? what are we talking about? The UPD Analyzers ADC input?
Basically I only ever use the 22KHz Bandwidth on the UPD (the UPD also has 100KHz & 350KHz spans) but the high frequency ADC used for these spans has a much poorer Dynamic range - so performance THD at 20KHz measurements would be pointless. The highest THD I can measure on the 22KHz span is 7.2KHz which gives me the 2nd and 3rd harmonics which can normally be expected to be the highest anyway.
The TI TAS5015 plot is a Digital input ClassD modulator, and the ESS9018 is a DAC, both of these are fed by the UPD's digital signal generator, so only the UPD's Analyzer (ADC) is used in the Analogue domain. For both these measurements there as no Analogue Generator.
With the TI TAS5015 you can see the shaped noise floor, with all harmonic components below the noise floor - the non harmonic spurie at around 6.7KHz is pickup of a CRT scan rate or some such, I never bothered hunting it down.
Yes--it surely has some sort of buffer ahead of the notch filter?
I actually ment 22 kHz BW, not 22 kHz fundamental.
It could well be that the harmonics of the source you're using (whatever that is) cancelled with the distortion contribution of the analyzer. I'm not saying this is what *must* have happened, but unless the performance of the analyzer is independently verified with a believable procedure, we need to keep this as a possibility.
Samuel
The Analyzers has the input stage not to mention the tracking filter itself - so ultimately these will limit the performance, but from experience -130dB Harmonics are not that hard to achieve, at around -140dB its getting interesting as basically everything starts to become nonlinear at these levels (Resistors, Capacitors used in integrators etc.) but once you encounter them you learn how to work with them.
Using the ESS DAC its possible to achieve -130dB Harmonics, but its Noise Shaper is rather messy and changing the level by a fraction of a dB results in a different distortion spectrum which is not a good sign.
Its possible to correct for these NS errors, but requires the use of a FPGA.
Interestingly its also possible to apply second order correction to model the ESS9018 DAC array resistor voltage coeff non-linearity and further improve the results.
I believe in this scenario its only possible to cancel even order components - I very much doubt you would be "lucky enough" to accurately cancel odd order non linearity - I speak from experience as we had to use second order modeling to correct for the Vcoeff of a resistor DAC array used in an ADC design - its not easy, and not by luck.
The Panasonic Industrial analyzer and the ShibaSoku 725 analyzer (and probably the audio-Precision 2722) are tracking filter analyzers and steered by the input frequency detected. The Panasonic I think is 2 tracking notch filters and the ShibaSoku 725 are three notch filters... Davada has improved the noise level on the monitor output port of the 725 such that at least 50dB more range can be seen with an FFT hung on the monitor.
Parts-wise, these are huge undertakings in design with parts counts similar to S.Groner's osc design. Now Davada has a very good osc design himself which does some impressive thd numbers and has much fewer parts to built it.
THx-RNMarsh
Parts-wise, these are huge undertakings in design with parts counts similar to S.Groner's osc design. Now Davada has a very good osc design himself which does some impressive thd numbers and has much fewer parts to built it.
THx-RNMarsh
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Sure but if you disintegrated the ICs there are probably more than 1800 parts.
JohnW
Is your classD amp similar to zetex (then Diodes ,CSR...) DDFA?http://www.diyaudio.com/forums/class-d/117627-zetex-ddfa.html
How do you subtract distortion component? Error feedforward and uses LPF inductor as summing component?
zetex's seems feedbacking it to digital side.
Is your classD amp similar to zetex (then Diodes ,CSR...) DDFA?http://www.diyaudio.com/forums/class-d/117627-zetex-ddfa.html
How do you subtract distortion component? Error feedforward and uses LPF inductor as summing component?
zetex's seems feedbacking it to digital side.