I'm showing my ignorance: wouldn't the servo have a good chance of munging up the LF noise performance? I thought this was designed around PSU analysis? Not in the least trying to be antagonistic (novel for me
), just trying to understand your aims.Rsavas: hope you feel better soon!
I'm showing my ignorance: wouldn't the servo have a good chance of munging up the LF noise performance? I thought this was designed around PSU analysis? Not in the least trying to be antagonistic (novel for me
Rsavas: hope you feel better soon!
There is a DC offset on the output limiting the full range value, so a servo can be designed to reduce this. The trick is to attenuate the servo output so it just gets rid of the offset and use filtering. A 1,000,000 ohm resistor feeding a 60 ohm input would have the noise of the 60 ohms not the 1,000,000 ohms. I
noise at zero Hz
I was looking for a new product announcement I thought I'd seen from TI for a chopper-stabilized amp, but so far found only the old TLC2652. It has a spec on peak-to-peak noise, with the conditions listed as spanning 0 Hz to various frequencies. I guess they consulted a clairvoyant for the zero frequency. Perhaps someone is still testing to verify.
I was looking for a new product announcement I thought I'd seen from TI for a chopper-stabilized amp, but so far found only the old TLC2652. It has a spec on peak-to-peak noise, with the conditions listed as spanning 0 Hz to various frequencies. I guess they consulted a clairvoyant for the zero frequency. Perhaps someone is still testing to verify.
Yes and it shows up almost exactly. What do you want perfect? At the noise levels this can resolve any source impedance above a few ohms limits the performance.
There has to be something better than brute force. I still have not had the time to try those Interfet parts, should do .2nV with negligible current noise and only 2 or 4 in parallel.
Bandwidth is 50 MHz. But are you saying building things with discretes is better than using ICs?
TSH300 has voltage noise density 0.65nV/sqrtHz and current noise density 3.3pA/sqrtHz, for 25 amplifiers equivalent voltage noise density 0.13nV/sqrtHz and current noise density 16.5pA/sqrtHz. The current noise will dominate if the source impedance (plus feedback resistor) is above 8 Ohm.
IF3602 is available from Mouser - more than 100 in stock
IF3602 is available from Mouser - more than 100 in stock
Easy to get I called they said how many and I sent a check (well I signed it). Eds way is just fine skinning cats and all.
The noise from a 6 ohm resistor is about .316 nV/rt Hz. If my math is right.
As the source I expect to look at is around .003 ohms current noise is not much of an issue.
The most expensive part was the PC board.
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hi marce/others,
been too sick to respond til now, sorry for that. thought I should respond so that you do not think your response had fallen on deaf ears. I'll keep this short as I can, i am running a fever. funny you mention 7400/4000 series logic and my mind is in eclips. some of these analog guys may have to look up eclips logic, it is mature but specialized technology.
jtag to me is a slow clocking system, but a valid one, as any other. jtag master clocks or scan clocks never go over 10MHz that I know of.
clock distribution networks is way off topic for this thread and audio forum.
Have you ever used hyperlynx SI? or any of the other SI tools (parasitic extraction of your pcb)? if not, i suggest that you get a hyperlynx demo going and try it out, it is really nice tool to use. I have not visited Cadence or Mentor ecad sites to get up to speed on all that is available today, but the basics remain the same. I used these tools now going on 20 years ago. it was sort of bleeding edge back then but i would think that it is or should be more the norm these days, that is if you are doing high speed designs, with tight timing margins(ps). without these tools you are at a huge dis-advantage as you say. We liked/tried our best to do "correct by design" pcb designs, similar to ASIC/IC design, full timing/SI simulation up front to try to minimize the surprises,costs,delays.
When I was doing pcb design for fibre channel networks, we routinely had 53MHz system clock, 36 bit data paths, yes 32 bit with 4 parity, for the parallel stuff that eventually got made into a serial stream, using a serdes in the 2-10Gb/s range. i know they are in the 20/40G range now.
the last big pcb design i did was 16 layers, all controlled Z, thin stackups for embedded capacitance to distribute low noise power supplies, nelco dielectric (gee I even remember the name of the stuff, i checked it is still around), it was a marvell in its day. So we had to do SI on all these pcb designs or we'd be dead in the water without sim.
so that is my bit of experience and history, just thought I'd get this out there for you or anyone else interested in high speed logic design. no need to respond and bore the slow edge rate analog guys with ps logic discussions, more important crap for you guys to discuss than how to design a pcb
Rick
I use Cadstar SIV these days, used Cadence in the past.
I did further my initial response, I hope you read that one, a few days ago now.
I mentioned jtag because although it is a slow clock it is a good example of a often widely distributed clock on a PCB and can cause issues when distributed to many devices, especially on limited layer PCBs.
Get well soon, illness is not fun.
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