Maybe i am mistaken, but i think the court confirmed most of carvers patent claims and rejected the interpretation favoured by velodyne and api .
The interesting point seems to be that Carver owned sunfire (producer of subwoofers and non-exclusive licensee of the patents) and tried to get compensation of estimated profit losses due to patent infringement.
That seems to be not possible.
I was not able to find some information; does anybody know what the result of the court proceedings was?
EMI has been much the same but HF/RFI is more variable. However, no matter where I have lived... I never had a problem with CM signals in my home audio system.
THx-RNMarsh
Last edited:
google scholar found nothing..
I am searching with no space between the words, as scott typed.
Marce, bcarso,
It dawned on me that the fanout I describe, that of pulling traces off the main branch and reducing the main width will indeed maintain signal integrity by preventing reflections at each branch connection. And as I think of it, only in one direction, exactly as Bcarso stated. Is this a common PC trace thing for clock distribution? I've never seen it.
John
I have a 200 ohmish line feeding five 3,000 ohm loads. So an end termination should clean things up a bit.
I figured it was a joke, but was surprised that google locked up. Then people started translating it for me..
I was wondering if the NSA had to decide whether to allow me to see the search results. They've been doing that lately since I started wearing the aluminum foil cap.. earthed of course, to the line cord small blade..
John
Wouldn't that change the impedance of the line at each tap? In turn the load will need to be adjusted to match each stub. I suppose you could model the whole array and see what happens. Not in any software I could afford. it would all be moot for frequencies below 1 GHz in audio applications. For clock distribution getting the electrical lengths uniform would be more important.
200 times five is a thousand ahmish.. that leaves you two thousand left over, bet you can raise lots of bairns with that much manpower in your neck of the woods..
Do they all wear straw hats?
Why do you suspect you need t-line "spuff" on an audio board?
John
Spuff = spiffy stuff.
google scholar found nothing..
I am searching with no space between the words, as scott typed.
Marce, bcarso,
It dawned on me that the fanout I describe, that of pulling traces off the main branch and reducing the main width will indeed maintain signal integrity by preventing reflections at each branch connection. And as I think of it, only in one direction, exactly as Bcarso stated. Is this a common PC trace thing for clock distribution? I've never seen it.
John
Preferable to Not branch clocks, using a clock distribution IC is far more preferable. As to other branches, DDR2 memory interface layout and Signal Integrity notes are a good source of how its done for high speed (2 stand alone DDR2 IC's not a DIM). If branching is done it can be handled by both simulation and using a high speed router, keeping the traces a constant impedance, avoiding layer changes and balance are the key, as well as the correct choice of termination, either series, parallel or both. Howard Johnson and Eric Bogatin's tomes are my guide here and the software.
For changing track widths and fancy copper shapes its the hard core RF guys you want to talk to....
https://www.jlab.org/accel/eecad/pdf/050rfdesign.pdf
Watched a guy doing it, tweaking the copper shapes to suite the design requirements, make high speed digital look like a breeze... its the true "Black Magic" of electronics and layout IMHO.
Simon7000, no problem, I'll keep the layout file and schematic I did, its in my play folder with a few other designs I played with. Would like to do a nice simple pre-amp sometime all SMD for fun and to see just how small you can go and still get good quality. It was a fun interlude and good practice.
Yes. Driving 5 200 ohm loads would start with a 40 ohm line, where it splits off one 200 ohm branch line the main drops width and is now 50 ohms, then 66.6, then 100 ohm, then a pair of 200's. It'd look like a 5 lane highway that drops to 4, 3, 2, then to 1.
Nah, just waitin for Ed to build it into his audio circuit..
Well, that's what squiggles are for. The electrons have to slow down in the hairpin turns.
Pfft...anybody can to that...
Now ya talkin.
edit:btw, the hardcore RF guys mainly do sine wave stuffs. The guys here are lost when trying to discuss single transition stuff.
John
Last edited:
a clk dist ic/ckt adds undesirable skew or prop delay, it degrades/eats into your timing margins. I am talking about a forwarded clock here.
clk dist ics are for distributing a system clock in a logic system, so that all the synchronous logic, being in the same time/clock domain get as close to possible a clock with minimal skew. you have to add the clock skew into your timing analysis.
I may date myself but these fundamentals stay the same.
sorry to say, I can think of one good reason, perpetuating non-sense, like when we had the discussion of the merits/reasons why one would spec telfon dielectrics for analog audio pcb fabrication for use in the home.
anybody ever use the old HP rf design s/w EEsoft?
Last edited:
Now that is tried and proven. Quick recovery btw
Well to nit pick, adding parts that are otherwise unnecessary, cost $ in pcb area, assembly/parts costs, every solder joint adds to the reliability numbers. so actually it can hurt, in a small way, thus in general it is bad engineering but if it is an experiment = not much to lose = fine by me
have fun with your transient analysis project using kHz waves. i think you will have de-skew your probes too I know I can be an a$$ at times.What the hell am i thinking TI is offering IBIS models, that is new to me
TAS5414-Q1 IBIS Model (Simulation Models)
Last edited:
I disagree, timing margins for most situations where a distributed clock is used is not that taxing... DDR memory is a different matter, but its controlled in the spec... having spent a lot of time debugging JTAG clock distribution and getting advice from some of the JTAG people we moved to proper clock distribution and removed the problems. Better to have a clean clock than try branches. If you timing is that critical then match the rest of the lines accordingly... If you are going to have a branched clock (or any signal) you also need the correct drive strength in the source gate.
Now that is tried and proven. Quick recovery btw
Well to nit pick, adding parts that are otherwise unnecessary, cost $ in pcb area, assembly/parts costs, every solder joint adds to the reliability numbers. so actually it can hurt, in a small way, thus in general it is bad engineering but if it is an experiment = not much to lose = fine by me
What the hell am i thinking TI is offering IBIS models, that is new to me
TAS5414-Q1 IBIS Model (Simulation Models)
Sorry I answered in haste as I was rushing for work and didn’t qualify my comment. If there are no signal integrity problems then branch routing for a clock is acceptable, it when you get signal integrity problems that it then becomes an interesting issue and as clocks get faster and signal rise and fall times fall it is becoming more problematic. For slow clocks with a sane rise & fall time it isn’t that much of an issue, as boards of 74/4000 logic with widely distributed clocks testifies too.
When you do get problems though with a clock it can be a nightmare to solve especially if you don’t have Signal Integrity software to both model the signal scenario or to run simulation on layout schemes to check their validity. If you have a clock that has to feed multiple devices such as JTAG the solution depends on numerous factors,, the number of branches, line impedance, driving devices current drive capabilities (the rise and fall time of the signal from the driver), receiving devices sinking ability, factors from the physical layout, possible crosstalk problems…. Trying to balance multiple braches of routes can be fun! Choosing whether to use series or parallel termination is the first task… For either resistor values have to be calculated then simulations run or trying different values and measuring with a scope etC. (the expensive and time consuming way when it’s not DIY).
Even using a clock distribution IC means resistor values have to be calculated and simulated for each clock line, but here the advantage is that the separate termination is isolated so changing one value wont un balance the other lines.
The best clocks are short sweat and go 10mm at most, not always possible. If you do run clocks round a board use the 3X rule for spacing, the ultimate version is 3X the dielectric between the clock signal and the adjacent ground plane, the rule of thumb version is 3X the normal track to track spacing, this minimises field coupling to adjacent tracks.
Guard rings… yes if they are wide, not as good according to some recent stuff I have read, will dig out the documentation and study more, but If I do remember guard areas with a width greater than 3X are desirable (it may be wider) otherwise they can couple adjacent lines to the clock trace, whereas having no guard track would have lower coupling effect as it is just space and no where for field lines to terminate. As said this is from some recent stuff I have been reading so confirmation is required.
Party time enjoy
.Even more party time fun is setting an interesting filter around the multicore/production power of ZZ live show....party time bigtime....hear them live like they ought to sound.
The next (major) act remarked on how good the sound was.....hmmmmm.....
Dan.
Last edited:
- Status
- Not open for further replies.