Moving forward. The amount of non-linear capacitance at the input of a solid state device changes with operating conditions. Change in input capacitance appears mostly to be connected with Vds in jfets. At least, the Toshiba audio jfets that we tend to use.
This CHANGE in input capacitance is a possible high frequency distortion generator. I have measured it, in the past. The amount of capacitance is important primarily in relation to the source impedance used. For example, a 100K input pot might be too much for a complementary differential Toshiba jfet input stage because the RinCin product would be too large. 10-20K might be preferred.
However, it is the CHANGE in input capacitance that really matters and this can be controlled by cascoding AND keeping a relatively high voltage (10-15V) across the input jfets (Vds). This minimizes the change in capacitance with signal.
This CHANGE in input capacitance is a possible high frequency distortion generator. I have measured it, in the past. The amount of capacitance is important primarily in relation to the source impedance used. For example, a 100K input pot might be too much for a complementary differential Toshiba jfet input stage because the RinCin product would be too large. 10-20K might be preferred.
However, it is the CHANGE in input capacitance that really matters and this can be controlled by cascoding AND keeping a relatively high voltage (10-15V) across the input jfets (Vds). This minimizes the change in capacitance with signal.
If this would be true, a common source JFET stage would be kinda ideal PIM generator.
Fortunately, the input capacitance has little to nothing to do with Vds. Cgd does, but that's already beyond what you are grasping at this point about JFETs
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It would also help you to get some understanding of how Ciss is defined and what's the relationship between Ciss and the input capacitance, as seen by the signal source in a common source JFET stage.
Larry Page and Serghey Brin have lots of information about Ciss.
That is correct, up to a "small" detail. Ciss is Cgs in parallel with Cgd when the drain and source are shorted. Somehow, I'm pretty confident that's not how you use your JFETs.
Anyway, Cgd does not change because of the input signal, but because of the changes in Vds as a result of the input signal. That's why cascoding helps. A simple example of causal relationship.
Sorry I dropped the ball on this after finding no consistent measurement setup. Toshiba, NXP, and Fairchild all have different graphs. The answer remains that one must extract Cgs and Cgd even for a pencil and paper analysis. As Syn08 said a common source amplifier with no gain is not to useful. Even with a cascode there is some residual Miller effect. The same FET as cascode on another still presents 2XCgd to the first FET (due to the -1 inversion).
By literal reading of the data sheet the 2SK170 would not be symmetrical???
By literal reading of the data sheet the 2SK170 would not be symmetrical???
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Do we have the 3 measurement procedures at least?
I could check a 2sk369, 389 and a BF862 under each regime with a HP4274A.
Gerhard
Is there an independent frequency component to the capacitance? I would think a Tek 130 would be ideal for these measurements. It was designed for measuring tube capacitances in circuit and has the driven shield necessary to measure a specific electrode.
Let me verify my superficial understanding of the cascode in this application. Please correct any misunderstandings here.
In a cascode, if the reference for the cascoding device is the source of the fet the gain would be very similar to that of the shorted s-d condition of the ciss measurement, except for the effect of the s-d voltage, unless the cascoding device has a low gm. (The drain V is lock to the source by the cascode device + a DC voltage.)
In a differential input at low frequencies the effective capacitance would be reduced by the feedback and gain of the system as it balanced by the rest of the amplifier or so my simple understanding suggests. However as the frequency increases and the available gain decreases the input capacitance would increase. This would be a linear effect if the amp is linear with frequency and voltage, and not if the amp is not.
Let me verify my superficial understanding of the cascode in this application. Please correct any misunderstandings here.
In a cascode, if the reference for the cascoding device is the source of the fet the gain would be very similar to that of the shorted s-d condition of the ciss measurement, except for the effect of the s-d voltage, unless the cascoding device has a low gm. (The drain V is lock to the source by the cascode device + a DC voltage.)
In a differential input at low frequencies the effective capacitance would be reduced by the feedback and gain of the system as it balanced by the rest of the amplifier or so my simple understanding suggests. However as the frequency increases and the available gain decreases the input capacitance would increase. This would be a linear effect if the amp is linear with frequency and voltage, and not if the amp is not.
WRT Cgs measurement, I'm thinking cascode device need to be referenced
but not impact gate of the test device.
Something like this should work.
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This is a good interview question, the resistance into an infinite resistor ladder. The answer is interestingly enough PHI (the golden mean) times R. It turns out the classical mathematical definition of PHI turns up in many problems with self similarity and large extent. It would be interesting to map all the artistic and architectural coincidences of PHI to a normal distribution and see if the mean is exactly PHI. It has been researched that many of the oft quoted Greek and Egyptian occurrences are not quite exact even though the simple geometric construct of circumscribing a pentagram with a five pointed star gives PHI exactly.
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