Jitter, Clock Distribution and Glue Logic

[Guido Tent]

IMHO the choice of the DAC chip & selection of chips each have 100x higher impact on what a little jitter ever could have.

Hi Bernhard

I find it hard to generalise, Some DACs are less sensitive to jitter than others

One should pay attention to all aspects, in a well balanced way

Your impact factor is not matching my experience though

best regards

 

[IanAS]

How about a tuned circuit after the output of the last gate?

I have this after a 74HCU04, simply a coil in series and a capacitor to + or deck. Trimmed for best sinewave shape.

This way there is no problem with leading edges as there aren't any.

I have three chips fed from this output.

Sounds sweet and full, good depth and width of image, nautral sounding.

I've not read of this on this forum. But it seems to work well.

 

[finneybear]

I'd like to have some info about that.

Hi Bricolo

This is just a number coming from our device modeling group. They have done lots of tests on Aglient jittering measurement machines. For system designers, we tend to use the bottom numbers to ensure everything is within the design specs. Not every 74HC04 gate is the same so do not bet on the optimal number.

-finney

 

[finneybear]

Re: Re: Re: Jitter, Clock Distribution and Glue Logic

Hi Finney

I generally agree with the remarks given above, but my jitter measurements on gates show lower values than you describe.

For a single inverter I can virtually see no additional jitter (I run into measurement limits) so these are around 2ps (I can hear them though

I measure jitter content between 10Hz and several kHz

Could you eleborate a little on your meaurement (method) ?

By the way, I looked at the AD9511: Their jitter spec is not stating BW.....

cheers

Hi Guido

I remember that you have Wavecrest machine, right? So it should peak out around 2ps. It's tricky to mesure the jitter impact of a logic gate. The load condition, the device variance, etc. 10ps is just the bottom line number we use. If my memory were correct, the number was measured under the condition that 4 fanout gates exist with certain capacitive load, clocking at 33MHz,etc.

I think somewhere in AD9511's datasheet states that the additive jitter is 255fs. Sure, it's based on the ECL logic so for pure CMOS, the number will be much worse than that.

-finney

 

[finneybear]

How about a tuned circuit after the output of the last gate?

I have this after a 74HCU04, simply a coil in series and a capacitor to + or deck. Trimmed for best sinewave shape.

This way there is no problem with leading edges as there aren't any.

I have three chips fed from this output.

Sounds sweet and full, good depth and width of image, nautral sounding.

I've not read of this on this forum. But it seems to work well.

Hi Ian,

I'd suggest you swap the HCU04 for a VHCU04 and see whether you can hear any difference. Trimmer is useful for putting the HCU04 in a better load condition; however, it wil not change the circuit limit of HCU04.

-finney

 

[finneybear]

Hi Bernhard

I find it hard to generalise, Some DACs are less sensitive to jitter than others

One should pay attention to all aspects, in a well balanced way

Your impact factor is not matching my experience though

best regards

Totally agree with Guido here. 100X is a bit exaggerated but I think we all know what Bernhard meant. Still, every extra pico second counts. Human ears are this sensitive.


-finney

 

[Joseph K]

Bricolo,

Originally posted by Bricolo

About the clock distribution: by using the "clean clock" as BCK for the DAC (instead of the BCK output from the decoder/filter) the new clock's edges aren't certainly synchronized to the other I2S lines's edges (normally, all I2S lines including BCK are coming from the same decoder/filter chip, so the edges occurs at the same time). Isn't this jitter too?

As it seems to be overlooked, I will try to answer this, and hope that the real deans here present will correct me..

It might be a problem. Maybe not so much as a jitter, but as a setup/hold hazard? A resolution would be to reclock all signals with the clean BCK, so they become synchronized [no, wrong word, aligned]. This would also decrease their jitter as well, which, as far as i understood, is a good point according both to Guido and Elso.
For doing this, you should deliberately introduce some delay between the clean BCK & the old I2S signals, for respecting the Dflop's Setup / hold requirements.

Ciao, George

 

[finneybear]

Bricolo,



As it seems to be overlooked, I will try to answer this, and hope that the real deans here present will correct me..

It might be a problem. Maybe not so much as a jitter, but as a setup/hold hazard? A resolution would be to reclock all signals with the clean BCK, so they become synchronized [no, wrong word, aligned]. This would also decrease their jitter as well, which, as far as i understood, is a good point according both to Guido and Elso.
For doing this, you should deliberately introduce some delay between the clean BCK & the old I2S signals, for respecting the Dflop's Setup / hold requirements.

Ciao, George

Yep, hazard is a better term to use here! Just came across this I2S re-clocking board a few days ago:

http://myweb.hinet.net/home1/wenyue/DSC04703.JPG

A CPLD is used to create a 3ns delay to make sure the bit data signal will be latched correctly. As far as the signals from CS8414, etc, are not way off, the outputs from this reclocking board will be as clean as you can get. Oh, and it's a 4-layer board.

-finney

 

[Bernhard]

Doesn`t all the logic inside the DAC, like seriell to parallel conversion introduce jitter too ?

 

[finneybear]

Doesn`t all the logic inside the DAC, like seriell to parallel conversion introduce jitter too ?

Any circuit will create new jitter. It's just how much jitter the circuit can tolerate.

For DACs, depends on what's inside, your mileage may vary. For instance, TDA1543 is a simple emitter current source based DAC. It's relatively immuned from jitter. For TDA1541, the upper 10bits are emitter current DAC, too, when the lower 6 bits are made of three 2-bit DEM(dynamic element matching) DACs. A DEM DAC needs a very precise clocking to make its theoretic advantage possible. Definitely this makes TDA1541 far more sensitive to external and internal jitters.

Most top DAC chips have either timing control elements or dynamic element matching thing inside. They are all very sensitive to jitter. Yes, in the meantime, these logics tend to introduce lots of new jitter, too. Yet remember that the logics are implemented in .5 or .35um geometry, the total jitter increased probably is still not as large as the one introduced by a 74VHC04 driving several gates.

-finney

 

[IanAS]

Are these chodrop emi absorbers any use?

http://www.chomerics.com/products/documents/emicat/pg183chodropemiabsorbers.pdf

Forgive such a simple question, but jitter, what exactly is it? Is is the slowing of rise time of a square wave? And rounding of it's leading edge? Or exaggeration into spiking of it's leading edge?

The thing with a tuned circuit is that it's not much if at all affected by the HCU04, etc, as the tuning is done after the gates and that makes a mostly smooth sinewave. I guess this then means that all the chips switch at the same time if they all switch at the same voltage. They'll switch at some point up the curve. So even for uneven length wires, the rise time and switching point might be the same as the rise time is so slow.

I know very little about the way these digital chips work so I don't pretend to understand this. But having tried several clocks, but not all, I found this unusual method sounds the best so far.

 

[Fin]

I'm thinking about clock distribution schemes; for a cd player mod. I know there are many possibilities, but I often read things here about using mutiple gates in one package/using both outputs of a gate/loading a gate with more than one input... relative to jitter.

I need a clock, feeding the decoder chip, the digital filter, and the dac (maybe divided by 4 if I go for non os). So 3 outputs, plus some if I want to try reclocking, or DEM reclocking on the 1541.

What bould be the right way to do this? Using the clock's output (certainly a Kwak Clock) to feed directly 4 chips? Connecting a buffer, then the 4 chips, 4 buffers... something else?

Back to the original question.....well, sort of......

Most seem to recommend directly clocking the DAC (TDA1541), the decoder and the filter. How important is it to directly clock the decoder (not through the filter)?

If a clock with four outputs is being used (like a Tent XO2.5 with three 11mhz and one 5.6mhz outputs), what is the best way to utilise these outputs? Obviously the 5.6mhz output would be used to directly clock the TDA1541. For the remaining three outputs, is it better to:

A. Use two of them to directly and separately clock the decoder and filter.

B. Use one output to clock the filter and decoder (decoder clocked through filter) and the remaining two outputs to relcock WS and DATA going to the DAC.

 

[Guido Tent]

Re: Re: Jitter, Clock Distribution and Glue Logic

Back to the original question.....well, sort of......

Most seem to recommend directly clocking the DAC (TDA1541), the decoder and the filter. How important is it to directly clock the decoder (not through the filter)?

If a clock with four outputs is being used (like a Tent XO2.5 with three 11mhz and one 5.6mhz outputs), what is the best way to utilise these outputs? Obviously the 5.6mhz output would be used to directly clock the TDA1541. For the remaining three outputs, is it better to:

A. Use two of them to directly and separately clock the decoder and filter.

B. Use one output to clock the filter and decoder (decoder clocked through filter) and the remaining two outputs to relcock WS and DATA going to the DAC.

Hi Fin

Clock the reclockers and the 1541 directly. The decoder + filter can be reclocked using a picogate buffer driven from XO2/5

best

 

[Fin]

Re: Re: Re: Jitter, Clock Distribution and Glue Logic

Hi Fin

Clock the reclockers and the 1541 directly. The decoder + filter can be reclocked using a picogate buffer driven from XO2/5

best

Hi Guido

So reclocking of the signals going directly to the DAC is most important?

Then - if there is enough space - make and install a small board with a picogate buffer and its own power supply - place it close to the decoder and filter.........?

The above will, no doubt, be the optimal solution.....but what if you have to make a choice? Which is the best compromise? Is it better to give the best clock signal to the decoder or to reclocking WS and DATA?

Most seem to go for direct clocking of the DAC, Decoder and Filter as a first line of attack..........and seem to regard reclocking of the other signals as a luxury. I like the idea of reclocking the other signals and wonder if direct clocking of the decoder is still important once this is done?

 

[Guido Tent]

Re: Re: Re: Re: Jitter, Clock Distribution and Glue Logic

Hi Guido

So reclocking of the signals going directly to the DAC is most important?

Then - if there is enough space - make and install a small board with a picogate buffer and its own power supply - place it close to the decoder and filter.........?

The above will, no doubt, be the optimal solution.....but what if you have to make a choice? Which is the best compromise? Is it better to give the best clock signal to the decoder or to reclocking WS and DATA?

Most seem to go for direct clocking of the DAC, Decoder and Filter as a first line of attack..........and seem to regard reclocking of the other signals as a luxury. I like the idea of reclocking the other signals and wonder if direct clocking of the decoder is still important once this is done?

It is most important to feed the reclockers with the cleanest clock, that is what I wrote

 

[Fin]

It is most important to feed the reclockers with the cleanest clock, that is what I wrote

Thanks Guido.....and sorry that I go on, and on, and on......until I fully understand.....but it is all clear now (I think)

So - the TDA1541A will be direct 1/2 clocked and the two 74HC74 reclockers will be directly clocked.....all from the XO2/5. The remaining clock output will feed the filter (which, in turn will feed the decoder). If there is enough space, I will install a picogate to separately clock the filter and decoder.


Now to the next stage:-

The existing clock, distribution and reclocking of BCK is based around a 74HCU04 inverter and a 74HC74 filp-flop. Using the XO2/5 means that these are no longer required for their original purpose - so I plan to swap the 74HCU04 inverter for a 74HC74 flip-flop, then use the two 74HC74s as the reclockers. It should only require some minor diversion of the WS and DATA signals to pass them through this two chips.


Now to the question:-

The existing layout has 390ohm series resistors in the three signal lines (BCK, WS and DATA) going to the TDA1541. Should these be retained, removed or replaced by 47ohm resistors?