I don’t think that Johnson should be a big problem.
I’m more worried about what “SpamBot” would think about such a design.
The (Aeff) R’s can be kept fairy low and the Johnson in the centre R evens out (as far as I remember)
I did some simulations a while ago. If you’re interested I’ll see if I can find the Pspice files and email them to you.
I was using the MAT devices.
I haven’t built the circuit yet (sorry Scott) I will do it.
And I agree it’s a complex circuit.
Cheers
Sorry can't decipher that!
btw the service date is due, time to maintain your nuts and bolts!
syn08 well put post!
http://www.diyaudio.com/forums/analogue-source/154394-hps-4-0-phono-stage-13.html#post1982869
Cheers Michael
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I'm slowly trying to understand the choices you made in your design syn08. As I am a beginner, I can't talk at the advance level you guys are usually discussing, so it's ok not to answer if you consider it's a waste of time. I got as far as the power supply for now.
My comment/question is about the pregs. You said the current draw is almost constant, so why aim for a shunt design. Also, if the current draw is small, your choice of mosfet is confusing to me, a beginner; I am wondering why you're using a 45A mosfet?
Also, on the one hand you used a super speedy opamp but on the other hand it drives a mosfet with high capacitance. This seems to me to sort of defeat the purpose, but it's possible I'm missing some important detail. Me thinking in very simple terms and lacking experience, I would have chosen some irf9610/610 to use as the shunt mosfet, with an order of magnitude smaller capacitance.
- A new power supply. While the opamps are fed from a standard pair of LM317/LM337 pair of regulators (so no more Jung superregulators), the low noise input stage (while still cascoded) is fed by a pair of onboard parallel regulators. The input stage draws low and almost constant current, so the parallel regulators (on board) can be designed for minimum power dissipation.
...
Meantime, comments are welcomed
My comment/question is about the pregs. You said the current draw is almost constant, so why aim for a shunt design. Also, if the current draw is small, your choice of mosfet is confusing to me, a beginner; I am wondering why you're using a 45A mosfet?
Also, on the one hand you used a super speedy opamp but on the other hand it drives a mosfet with high capacitance. This seems to me to sort of defeat the purpose, but it's possible I'm missing some important detail. Me thinking in very simple terms and lacking experience, I would have chosen some irf9610/610 to use as the shunt mosfet, with an order of magnitude smaller capacitance.
Don't bother, it's obviously not for you, your high end gurus are your best bet. The choices are based on physics and EE and HPS 4.0 is not intended to be sent for reviews or otherwise commercialized.
- For constant curent consumption, a shunt regulator can be designed to minimize the power dissipation.
- Sometimes you work with what's at hand if it's good enough. It happens I have a stock of those MOSFETs that I got for free from OnSemi.
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Cleaned out a lot of personal mudslinging. Consider this an official warning that any more will result in Bin time. Some of it may already have done so.
Ok, it seems like I was not clear enough.
So why/when is a parallel regulator good when it comes to power dissipation? Assume a gain stage that requires 10V and it takes a constant 1A current (say, a SE class A amp). If the current is constant, then the shunt regulator can be designed for a regulator device current of 1A plus a margin of 10%. Now, under normal operation, the regulator will dissipate a power of only 10V*(1.1 - 1) = 1W. Also, the parallel device is well protected against SOA failures, since the worst case is the "no load" situation, unlikely to ever happen. A practical conclusion: always place a fuse before a shunt regulator, you'll save some trouble
Now, assume a class AB gain stage, taking an average current of 300mA and a peak current of 1A. The same parallel regulator (it has to be able to deliver the peak current, otherwise the output voltage will drop) will now dissipate, under normal operating conditions, 10*(1.1 - 0.3)=8W
If you now consider a serial regulator, assuming a minimum of 3V drop on the serial regulator, in the first case you'll have a 3*1 = 3W dissipation, while in the second case you'll have 3V*0.3 = 0.9W
This is of course a gross approximation. I did not consider the ballast resistor (or current source) power dissipation and the input voltage source impedance. But certainly, parallel regulators are better when the current drawn is constant.
Now, to the HPS 4.0 point. If the parallel regulator would feed the entire head amp (including the OPA552 opamp) then it should be designed to deliver a minimum of 300mA. That's because at 8V output (see my previous long post about headroom considerations) the opamp needs to deliver 200mA in the feedback network. Also, the input follower and the gain stage takes some (constant) 100mA.
Under normal operations though, the output signal is 40*0.5mV = 20mV (40 is the headamp gain), that is, only 0.5mA in the feedback network. The OPA552 needs some 10mA by itself, so the total current drawn from the power supply is, say, 110mA. A parallel regulator feeding the entire head amp will dissipate on average about 17V*0.3 = 5.1W, while one that's feeding only the input follower and gain stage will be 17V*0.12 = 2W That's a significant power saving, meaning less heat around the low noise input stage. The ballast resistor can be placed far away from the critical circuitry.
Now, regarding the high current MOSFET and choosing an opamp. It's pretty obvious that in a parallel regulator, the device linearity should be a second concern. The Ciss (input capacitance) of a MOSFET device is though certainly important for defining the AC behaviour of the regulator. However, as long as the error amplifier is able to provide enough current to drive the gate, it is the combination of gate resistor and Ciss that defines the AC behaviour, by inserting a dominant pole in the loop gain, defining the unity loop gain frequency. Provided (again) that the error amp is able to drive the gate current (and BTW, this is a large signal problem, AC response is a small signal discussion), there's not much of a difference between a MOSFET with Ciss=1nF and a 10ohm gate resistor, vs. another one with Ciss=100pF and a 100ohm gate resistor. Again, what really matters is the unity loop gain frequency and the single (dominant) pole behaviour.
Regarding the opamp. THS4031 was not in particular chosen for the speed, but for a) the current drive capability, b) the high open loop gain (or GBW product), c) the low noise and, last but not the least, d) availability (TI is pretty generous with the engineering samples). It delivers up to 150mA and has a full power bandwidth of 7MHz! That's going to ensure that actually the MOSFET and it's gate capacitance will set the unity loop gain frequency and keep the regulator unconditionally stable.
I've lauched this challenge before: come up with a better performance at a reasonable complexity, this regulator takes less than 1 sq. inch on the board. Using discrete devices makes sometimes sense (e.g. when it comes to ultra low noise, or high power output stages, etc...) but otherwise there's little reason (other than educational) to go that route.
Slowly towards the HPS 4.0 final implementation...
Power supplies completed and tested (schematics (one channel) and photo (both channels) are attached).
Key performances, using LME49810:
- Output noise: < 8nV/rtHz @ 1KHz
- Output impedance (measured as described in http://cp.literature.agilent.com/litweb/pdf/5968-7274E.pdf)
4mOhm @ 1KHz
11mOhm @ 100KHz
57 mOhm @ 600KHz
- Unity loop gain frequency: 2.6MHz
- Phase margin: 94 degs
(With 33pF compensation, both measured as described in the same HP document).
Line and load regulation: > 90dB (my measurement dynamic range limit).
Output spurious, 100mA load switching: < 50uV
I'll redo the measurements with other opamps (OPA637, THS4031, etc...), although the current results are already better than the design target.
Power supplies completed and tested (schematics (one channel) and photo (both channels) are attached).
Key performances, using LME49810:
- Output noise: < 8nV/rtHz @ 1KHz
- Output impedance (measured as described in http://cp.literature.agilent.com/litweb/pdf/5968-7274E.pdf)
4mOhm @ 1KHz
11mOhm @ 100KHz
57 mOhm @ 600KHz
- Unity loop gain frequency: 2.6MHz
- Phase margin: 94 degs
(With 33pF compensation, both measured as described in the same HP document).
Line and load regulation: > 90dB (my measurement dynamic range limit).
Output spurious, 100mA load switching: < 50uV
I'll redo the measurements with other opamps (OPA637, THS4031, etc...), although the current results are already better than the design target.
Looking great!
I assume that "LME49810" below is a typo. It is "LME49710" in your schematic.
I assume that "LME49810" below is a typo. It is "LME49710" in your schematic.
Maybe (I doubt it's simpler though) however, from a performance perspective, even a 22 ohm resistor is already doing great.
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