At the risk of burdening you with finding another way to disagree with me, I shall agree with you.
When I read you two points they don't seem to disagree with what I wrote but if you think they do then I shall elect to disagree with myself.
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What a pitty, I have seen and realized this just today. BTW, I am contributing a little these days.
I'm specifically refering to high voltage BJT transistor minority carrier diffusion in the base region (several um thick, not 100nm of small signal Q or even less for IC),
b-e displacement current doesn't control BJT collector current - minority carriers do
even 10s of nS isn't direclty limiting for audio frequencies - but does partially determine the loop gain avaliable at audio frequencies by limiting the loop gain intercept frequency for desired stability margins
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One must define a phase margin at some frequency and referenced it to another frequency say 1 kHz. Thus the phase margin over the audio band is x degrees.
One can probably also look at it another way, in asking what is the phase at zero gain which would directly impact on the stability of the circuit driving complex loads. Let us assume that the phase changes to 180 degrees before the amp gain reached zero dB then the feedback will be positive and the amp oscillates.
What are we referring to?
One can probably also look at it another way, in asking what is the phase at zero gain which would directly impact on the stability of the circuit driving complex loads. Let us assume that the phase changes to 180 degrees before the amp gain reached zero dB then the feedback will be positive and the amp oscillates.
What are we referring to?
Hi Nico,
The concepts of phase margin and gain margin are covered in depth in my book "Designing Audio Power Amplifiers" just out in September by McGraw-Hill. You can see the table of contents and other information about the book on my website at CordellAudio.com - Home.
Put rather simply, phase margin is determined by the phase around the complete feedback loop at the frequency where the loop gain around the complete feedback loop is 0 dB. If the phase around the loop is 130 degrees at this frequency, then the phase is 50 degrees away from the value of 180 degrees that will cause oscillation, so in this case the phase margin is 50 degrees.
Cheers,
Bob
Hi Bob,
Even if the phase inversion occurs at a frequency much higher than the zero dB gain a complex load could shift the phase inversion to be inside the amp gain loop and it will oscillate.
This is not just applicable to audio, it is universal to any gain block that uses negative feedback. Even in gain blocks that does not use negative feedback but there are sufficient coupling through parrasitic and other stray elements. At audio frequencies this is a simple matter to solve.
Kindest regards
Nico
Even if the phase inversion occurs at a frequency much higher than the zero dB gain a complex load could shift the phase inversion to be inside the amp gain loop and it will oscillate.
This is not just applicable to audio, it is universal to any gain block that uses negative feedback. Even in gain blocks that does not use negative feedback but there are sufficient coupling through parrasitic and other stray elements. At audio frequencies this is a simple matter to solve.
Kindest regards
Nico
Hi Nico,
I think that all you are saying here is that a complex load could cause increased phase lag such that the 180 degree point lies at a frequency where the loop gain is greater than 0 dB, and this is certainly correct.
Phase margin will almost always be some function of the load impedance. It will also be affected by output voltage and output current.
Cheers,
Bob
Bob,
Of course.
Phase margin may be only indicative to stability but is not a given that phase margin of 50 degress is good or 25 degrees is bad. There are more to this I believe. You may design for a phase marging of 70 degrees but the phase change over the audio band is 50 degrees, could this be acceptable.
Cheers
Nico
Of course.
Phase margin may be only indicative to stability but is not a given that phase margin of 50 degress is good or 25 degrees is bad. There are more to this I believe. You may design for a phase marging of 70 degrees but the phase change over the audio band is 50 degrees, could this be acceptable.
Cheers
Nico
70 degrees from UG point ??? Oscillator ... maybe not always , but into a sufficient capacitive load while doing a standard transient analysis ..Yup. (attachment 1/2). I under-compensated the standard "blameless" (AX1 - 3'rd pix BODE) with 1 and 10 uf loads @ 70/65dg. margin. I go for 80-82dg. at UG , never a warm zoble - good 20KHZ square wave.
At 70dg. I have observed random oscillation , not enough to "blow"
, but enough to feel (zoble warm) and see on my 20mhz CRO.
4th attachment is what I "shoot for" and is what a house full of working amps rely on.
BTW , this is how andy C. /GK taught me .. and has served VERY well.
OS
At 70dg. I have observed random oscillation , not enough to "blow"
, but enough to feel (zoble warm) and see on my 20mhz CRO.4th attachment is what I "shoot for" and is what a house full of working amps rely on.
BTW , this is how andy C. /GK taught me .. and has served VERY well.
OS
Attachments
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stability
I ran your circuit and looked at loop gain...you still have 80 degrees of phase margin if you change C5 from 1n to 0 and reduce C1 from 100 pF to 47 pF. It makes your 10 kHz distortion drop so that all harmonics are 100 dB below fundamental with 26 volts peak to peak output. With your original values, the even harmonics were 100 dB down, but odd harmonics were only down about 87 dB.
Now, I haven't run some of the torture tests for stability, but it seems to be a pretty conservative compensation.
I ran your circuit and looked at loop gain...you still have 80 degrees of phase margin if you change C5 from 1n to 0 and reduce C1 from 100 pF to 47 pF. It makes your 10 kHz distortion drop so that all harmonics are 100 dB below fundamental with 26 volts peak to peak output. With your original values, the even harmonics were 100 dB down, but odd harmonics were only down about 87 dB.
Now, I haven't run some of the torture tests for stability, but it seems to be a pretty conservative compensation.
what frequency is the oscillation? How strong?
OK...so we're talking about real hardware, not simulation...
What frequency is the oscillation? How strong? With a load? Without a load? What kind of load makes it oscillate worse? When driven hard? When hardly driven? With input shorted? With input open?
The question is, is it a loop (e.g. around the whole amp loop), or is it more localized? Sometimes just the output pairs will oscillate by themselves...e.g. Q13-Q15, or Q12-Q14.
Here's a way to separate the issues...If it's a loop thing, then increasing the gain should make it oscillate less. Change R15 from 1K to 500 Ohms...The gain will about double, but the oscillation, if based on loop stability issues, should calm down.
OK...so we're talking about real hardware, not simulation...
What frequency is the oscillation? How strong? With a load? Without a load? What kind of load makes it oscillate worse? When driven hard? When hardly driven? With input shorted? With input open?
The question is, is it a loop (e.g. around the whole amp loop), or is it more localized? Sometimes just the output pairs will oscillate by themselves...e.g. Q13-Q15, or Q12-Q14.
Here's a way to separate the issues...If it's a loop thing, then increasing the gain should make it oscillate less. Change R15 from 1K to 500 Ohms...The gain will about double, but the oscillation, if based on loop stability issues, should calm down.
I dont have an oscilloscope or a waveform generator to test the amp.with a speaker connected at the output and when there is signal at the input from an mp3 player the current consumption is normal ..today i replaced the output speaker with a resistor of 8 ohm in parallel with a 2.2μF capacitor and input from an mp3 player. the amplifier was oscillating for sure because there was 1A of current at the ammeter (i use a transformer which gives max 1 ampere.)
In his post on the first page of this thread Bod Cordell says "This measurement must be performed absent any input low-pass filtering on the amplifier."
I have been working on design in SPICE and my findings there had raised two potential issues with this statement.
I will post some images of the circuit to illustrate by points and would be glad of any feedback from the cognizanti here to see If my theories hold up.
1) I have noticed that simply removing any input filter will often not be sufficient to get accurate results.
Here is the circuit - A version of the 1969 JLH Simple Class A with LTP, Mosfet o/p and bypassed 100uF film caps in the FB & bootstrap positions.
It's design with low gain so that it can be driven directly from the DAC without too much loss of Bit Depth.
As we are measuring Gain Phase margins to and assess the stability of the FB loop I concluded that the appropriate places to measure the I/P phase would be at the base of the i/p transistor but I noticed that with the I/P filter cap removed, the phase ( at the frequency where the CLG dropped to 0db - 6.7MegHz ) was already -26.69 degrees.
So from then on I proceeded to take the difference between the phase at the I/P of the FB loop and the phase at the O/P.
The phase that o/p was -127.69 but because we had already lost 26.69 degrees, the net lag within the FB loop was only 100.98 degrees - see image below:
So my first conclusion was that just taking out the i/p cap was not sufficient as a substantial phase lag is created just because of the combined resistance of the DAC o/p & the Amp i/p resistance. So for a real life estimate of phase margin I concluded that it is best to include the expected series resistance and measure phase difference from I/P to O/P of the FB loop with those in place.
But this was only the minor part of the problem . . .
I have been working on design in SPICE and my findings there had raised two potential issues with this statement.
I will post some images of the circuit to illustrate by points and would be glad of any feedback from the cognizanti here to see If my theories hold up.
1) I have noticed that simply removing any input filter will often not be sufficient to get accurate results.
Here is the circuit - A version of the 1969 JLH Simple Class A with LTP, Mosfet o/p and bypassed 100uF film caps in the FB & bootstrap positions.
It's design with low gain so that it can be driven directly from the DAC without too much loss of Bit Depth.
As we are measuring Gain Phase margins to and assess the stability of the FB loop I concluded that the appropriate places to measure the I/P phase would be at the base of the i/p transistor but I noticed that with the I/P filter cap removed, the phase ( at the frequency where the CLG dropped to 0db - 6.7MegHz ) was already -26.69 degrees.
So from then on I proceeded to take the difference between the phase at the I/P of the FB loop and the phase at the O/P.
The phase that o/p was -127.69 but because we had already lost 26.69 degrees, the net lag within the FB loop was only 100.98 degrees - see image below:
So my first conclusion was that just taking out the i/p cap was not sufficient as a substantial phase lag is created just because of the combined resistance of the DAC o/p & the Amp i/p resistance. So for a real life estimate of phase margin I concluded that it is best to include the expected series resistance and measure phase difference from I/P to O/P of the FB loop with those in place.
But this was only the minor part of the problem . . .
Then I thought I would repeat this process with the input cap in place using the same method as it's phase lag could simply be subtracted from the O/P phase lag to give the net phase lag with the FB loop, the thinking being that leaving the I/P cap in place was the actual circuit that would be in use during listening.
In the Image below you can see the the two measurement points . . .
. . . and above we can see the results with I/P cap in place. Now the phase lag at the FB loop I/P is -80.16 degrees and the phase lag at the O/P is -134.46 degrees.
But now, the net phase lag within the FB loop is only -54.3 degrees. A whopping 46.69 degrees less than was predicted in the circuit with the I/P cap removed.
If the above process is valid then it would seem that it is much more accurate to measure the phase lag with the I/P cap in place.
Obviously one question would be can we trust these SPICE results but putting that to one side I would very much like to hear your comments on the validity of this measurement technique whether in SPICE of in real world testing.
thanks
mike
In the Image below you can see the the two measurement points . . .
. . . and above we can see the results with I/P cap in place. Now the phase lag at the FB loop I/P is -80.16 degrees and the phase lag at the O/P is -134.46 degrees.
But now, the net phase lag within the FB loop is only -54.3 degrees. A whopping 46.69 degrees less than was predicted in the circuit with the I/P cap removed.
If the above process is valid then it would seem that it is much more accurate to measure the phase lag with the I/P cap in place.
Obviously one question would be can we trust these SPICE results but putting that to one side I would very much like to hear your comments on the validity of this measurement technique whether in SPICE of in real world testing.
thanks
mike
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If the above approach is valid it is quite revelation for me. I had always assumed that adding an i/p filter would have little or no impact on loop stability.
Now, perhaps it would seem that i/p filters can play a part in achieving good phase margins - or rather they always did, but some of us just hadn't realised it.
BTW with the above circuit SPICE predicted that the gain margin was about -62db when the net phase was -180 deg @ about 35Meg Hz but I know that in real life this frequency will be much lower.
Now, perhaps it would seem that i/p filters can play a part in achieving good phase margins - or rather they always did, but some of us just hadn't realised it.
BTW with the above circuit SPICE predicted that the gain margin was about -62db when the net phase was -180 deg @ about 35Meg Hz but I know that in real life this frequency will be much lower.