This circuit is meant to be driven from a conventional PWM generator. There are two events that turn on a mosfet: The current flowing through the upper diode and a pulse generated by a not-shown circuit at turn-on. The flip-flop is turned off by the PWM generator.
The idea is pretty simple: It is a conventional PWM amplifier, however in this case the PWM generator turns off one mosfet by reseting its gate flip-flop, but it does not turn on the other mosfet. When the current through the mosfet is stopped, the current flowing through the inductive load attached to the drains does not stop. This current charges the 50/60 pF capacitance attached at the drains, until the drain voltage reaches the opposite rail. At this point the other flip-flop is set and the other transistor starts conducting. This means there are essentially no switching loses as the transistors are always turned on at zero voltage. In case the resonant behavior is lost due to a inadequate load or input, the voltage at the drains will not reach the upper mosfet and therefore the circuit will lock.
At 250 KHz, 200 mA current and 50% duty cycle, the switching time would be around 250 nS. The circuit would spend 500 nS switching with no loses and 1.75 microseconds conducting from each rail. At 50% duty cycle, once the turn-on condition has happened (meaning the voltage at the drain of the mosfet has reached the source rail) the current will take 875 ns to reverse. This means the flip-flop can have a comfortable propagation delay without introducing any kind of artifact. With some pulse width modulation this requirement will be more strict but well within what's attainable with conventional parts. The gate drive circuit does not see any high voltage.
EDIT: The clock input is a spice artifact. The circuit will not use a clocked flip/flop. I just did not realize the part symbol had a clock input until it was too late.
I will be careful when debugging the circuit but this sounds quite far from now.
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You might need an initial pulse to get it started.
Absolutely.
Good to see you've had a good experience with an SMPS
I will post the results but I don't think i'll have anything soon as it's a long term project.
Won't you achieve the same ZVS behaviour with just carefully trimmed dead time or dead time which is high enough?
Sounds much more rugged to me and in case of no ZVS conditions the signal is still there, with just one hard switching of Qoss.
Your proposal is certainly simpler. However in case of no ZVS it is better to switch it off unless its for a really short interval because the output transistors aren't going to stand it for long. The use of a long dead time has two potential problems that I will check. The first one is that it's not obvious if the longest switching time is still shorter than the fastest current reversal time. The second is what happens when the amplifier is powered on. With the flip-flop design the amplifier can be left in a "standby" mode with both transistors powered down until all the supply voltages have stabilized. This is a very good comment nonetheless and I will give it some serious thought.
Thanks, anyway I wouldn't worry that much about ZVS, it is probably going to work that way or another or get 'nearly zero voltage switching'.
One thing that needs more focus is switch-off characteritics in my opinion.
First, you have to switch the mosfet off quite brutally so that it is completely off when Vds starts sloping towards the other rail, this means charging Qs much faster than inductor current (dis)charges Qoss. Otherwise the turn-off is hard even if switch-on is soft.
The second thing is keeping the stuff off and not letting miller-induced false switch-on's.
The fast 2500V voltage slope is likely to mess with gate driving scheme by miller effect.
In my humble opinion negative turn-off gate drive with low impedance driver is absolutely mandatory here, adding an extra external gate-source capacitance is also an option (to 'clamp' the miller spike into the increased Cgs). +-15V gate driving shouldn't be a problem.
One thing that needs more focus is switch-off characteritics in my opinion.
First, you have to switch the mosfet off quite brutally so that it is completely off when Vds starts sloping towards the other rail, this means charging Qs much faster than inductor current (dis)charges Qoss. Otherwise the turn-off is hard even if switch-on is soft.
The second thing is keeping the stuff off and not letting miller-induced false switch-on's.
The fast 2500V voltage slope is likely to mess with gate driving scheme by miller effect.
In my humble opinion negative turn-off gate drive with low impedance driver is absolutely mandatory here, adding an extra external gate-source capacitance is also an option (to 'clamp' the miller spike into the increased Cgs). +-15V gate driving shouldn't be a problem.
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