I'm experimenting with composite power-opamps and would like to know is it absolutely essential to have output power opamp (wired as an integrator in both circuits) much faster than input opamp for stability? Are the circuits in image stable or not according to the simulation?
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do they work in .TRAN with t_max_step << 1/GBW of the fastest part?
the slower output amp does limit the gain you can add with the input amp - heavy compensation on the input/servo op amp can keep the loop stable - but its not safe to try to push the loop intercept beyond what the output/slowest amp in the loop can do safely by itself
the slower output amp does limit the gain you can add with the input amp - heavy compensation on the input/servo op amp can keep the loop stable - but its not safe to try to push the loop intercept beyond what the output/slowest amp in the loop can do safely by itself
I'd use 5-10 ns, 1/19MHz ~ 50 ns, 10 points per cycle would be enough to show major loop oscillation
with my new this year PC even 1-2 ns works at acceptable sim speed depending on circuit complexity - models aren't usually any good for those frequencies though
I'd pick the input op amp for its noise, input type, linearity - then compensation around the input op amp is adequate to stabilize the loop if the input op amp itself is "too fast"
the gain/phase plots are helpful - to the extent the spice models are representative of the real parts - not always the case
read the data sheet for minimum GBW, look at the graphs for phase, scale in the worst direction by the ratio of the typ to min datasheet numbers
step response may have overshoot with the higher order compensation - so the usual trimming for "good" step response won't work as well with these type composite amps - the transients/settling tail should be well separated from audio frequencies, the step overshoot killed in the system with a input low pass (200 kHz low pass is considered inaudible even by many audio gurus)
with my new this year PC even 1-2 ns works at acceptable sim speed depending on circuit complexity - models aren't usually any good for those frequencies though
I'd pick the input op amp for its noise, input type, linearity - then compensation around the input op amp is adequate to stabilize the loop if the input op amp itself is "too fast"
the gain/phase plots are helpful - to the extent the spice models are representative of the real parts - not always the case
read the data sheet for minimum GBW, look at the graphs for phase, scale in the worst direction by the ratio of the typ to min datasheet numbers
step response may have overshoot with the higher order compensation - so the usual trimming for "good" step response won't work as well with these type composite amps - the transients/settling tail should be well separated from audio frequencies, the step overshoot killed in the system with a input low pass (200 kHz low pass is considered inaudible even by many audio gurus)
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Great, thx for all pointers...I'll try to digest as much as I can and come back for more.
Regarding input opamp type, I would prefer to use J-fet input opamp, if I can get away with higher noise on the output, also would like it to have input circuit like OP627/637 (Rush cascode), AD825 (Rush cascode + folded cascade) or AD744 (pin for external compensation could be useful). I'm not familiar with the latest offering from TI/NS and LT...do you have any recommendation in that regard?
Regarding input opamp type, I would prefer to use J-fet input opamp, if I can get away with higher noise on the output, also would like it to have input circuit like OP627/637 (Rush cascode), AD825 (Rush cascode + folded cascade) or AD744 (pin for external compensation could be useful). I'm not familiar with the latest offering from TI/NS and LT...do you have any recommendation in that regard?
With a bit of trepidation, and given I hijacked a bunch of jcx's ideas, I offer my (present) composite idea. Still a bit of a ways to go (servo, probably a balanced line receiver, power decoupling, etc), but here's what I'm thinking so far. Would love any comments, etc. Seems to pass a square wave fairly well, but of course I'm using a dummy macromodel of the 7293 that is hopefully pessimistic enough!
It's hard to get any gain into that outer loop with the loop intercept where it is, or whether it's even worth using that 180pF on the 7293's inner loop versus just running it straight at G=20.
It's hard to get any gain into that outer loop with the loop intercept where it is, or whether it's even worth using that 180pF on the 7293's inner loop versus just running it straight at G=20.
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Hi
Wish I could think of a more tactful way to say it but the results look "sub-optimal".
I would call the PM as unacceptable, or close, for an audio amp and the GM unacceptable.
Especially for only 40 dB of gain @ 20 kHz, that should be obtainable far more simply.
Best wishes
David
David,
No need for worrying about tact (although you were!), I appreciate candid responses and am eager to learn.
That small a loop gain and phase margin that's what I'm sitting here worrying about. Now, admittedly, I made the macromodel for the TDA7293 by reading between the lines of their rather-sparse datasheet (their Avmin is spec'd at G=20, so I worst-case scenario'd it at 45* of phase margin), and their nominal Avol is spec'd at 80 dB, so I underrated it by 20 dB to assume, again, a worst case scenario. UGBW is not even specified, and measurements around the internet are veritably sparse, so I picked 2 MHz, given the low end of where a fair number of chip amps converge. Perhaps someone around my uni department has the right stuff that I could measure my chips in circuit--time to see who's in a high speed analog group.
Re-configuring the macromodel for Avol = 80 dB and with a UGBW of 8 MHz (maintianing G=20 @ 45* PM) improves the outer loop's phase margin by ~15 degrees and throws (at 20k) about 15 dB more gain into the outer loop and about 10 dB more into the TDA7293's inner loop. And that's without adjusting the specified caps, which are obviously killing all the bandwidth. I'll see if I can get on the computer that has this more optimistic theoretical model and show what *should* be a much better design. But, yes, it does seem that I'm trying to squeeze blood from a stone with the above macromodel. It doesn't help I've chosen to run it underneath its minimum recommended gain, either.
I'd prefer to run the system at Av of around 13, since the signal source is hot enough to drive into clipping with 35 vdc rails. I already have the 7293's and an appropriate transformer, as they were given to me from a logitech z680 whose controller died. Trying to see if I can materially improve on the bog standard layout of it in non-inverting.
So, with that, I'm all ears for suggestions (critical especially). It's looking more and more like Panson's solution to using the LME49811 as a driver for the 7293's OPS might be a better solution.
No need for worrying about tact (although you were!), I appreciate candid responses and am eager to learn.
That small a loop gain and phase margin that's what I'm sitting here worrying about. Now, admittedly, I made the macromodel for the TDA7293 by reading between the lines of their rather-sparse datasheet (their Avmin is spec'd at G=20, so I worst-case scenario'd it at 45* of phase margin), and their nominal Avol is spec'd at 80 dB, so I underrated it by 20 dB to assume, again, a worst case scenario. UGBW is not even specified, and measurements around the internet are veritably sparse, so I picked 2 MHz, given the low end of where a fair number of chip amps converge. Perhaps someone around my uni department has the right stuff that I could measure my chips in circuit--time to see who's in a high speed analog group.
Re-configuring the macromodel for Avol = 80 dB and with a UGBW of 8 MHz (maintianing G=20 @ 45* PM) improves the outer loop's phase margin by ~15 degrees and throws (at 20k) about 15 dB more gain into the outer loop and about 10 dB more into the TDA7293's inner loop. And that's without adjusting the specified caps, which are obviously killing all the bandwidth. I'll see if I can get on the computer that has this more optimistic theoretical model and show what *should* be a much better design. But, yes, it does seem that I'm trying to squeeze blood from a stone with the above macromodel. It doesn't help I've chosen to run it underneath its minimum recommended gain, either.
I'd prefer to run the system at Av of around 13, since the signal source is hot enough to drive into clipping with 35 vdc rails. I already have the 7293's and an appropriate transformer, as they were given to me from a logitech z680 whose controller died. Trying to see if I can materially improve on the bog standard layout of it in non-inverting.
So, with that, I'm all ears for suggestions (critical especially). It's looking more and more like Panson's solution to using the LME49811 as a driver for the 7293's OPS might be a better solution.
OK! That makes it worth the effort to look more carefully at your work.
So I now notice that your probe placement is incorrect.
The feedback splits after the TDA7293 macro-model, you need to put the probe in the circuit before the split, in other words immediately after the controlled source.
Try that and post the results, perhaps some of your problems are only due to bad data, certainly essential before any more work.
Best wishes
David
Pictures are less cluttered if you turn off the grid,
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Round 2: major differences are:
1.) I slightly relaxed the constraints (model assumes about 52 degrees PM when the TDA7293 is used, without any compensation, at G=+20)
2.) No integrator on the TDA7293. This alleviates JCX's DC convergence issue (even though using the macromodel makes it an effective farce).
3.) Stabilizing the TDA7293 into G=+13 with lead compensation. May not match up with reality.
4.) 2nd order integrator on the input opamp pushes its forward gain at 20 kHz much higher. This leaves me concerned about its stability (even if spice is okay with it...)
The "guessed" endpoints to the TDA7293 are modeled: (both modeled as 55 degrees PM @ G=+20)
1. GBW=2 MHz, Avol=60 dB
2. GBW=8 MHz, Avol=80 dB
The amount of lead compensation one needs decreases with the higher GBW model, so that's the only change made in the two .asc's attached. I, understandably, pushed the lower GBW model, leaving a lot of loop gain on the table for the higher GBW model, but without knowing what I have, it's *hopefully* a safer bet.
Putting the probe anywhere on the outer loop yields the same result.
Comments/critiques appreciated! I'm here to learn.
Thanks,
Daniel
1.) I slightly relaxed the constraints (model assumes about 52 degrees PM when the TDA7293 is used, without any compensation, at G=+20)
2.) No integrator on the TDA7293. This alleviates JCX's DC convergence issue (even though using the macromodel makes it an effective farce).
3.) Stabilizing the TDA7293 into G=+13 with lead compensation. May not match up with reality.
4.) 2nd order integrator on the input opamp pushes its forward gain at 20 kHz much higher. This leaves me concerned about its stability (even if spice is okay with it...)
The "guessed" endpoints to the TDA7293 are modeled: (both modeled as 55 degrees PM @ G=+20)
1. GBW=2 MHz, Avol=60 dB
2. GBW=8 MHz, Avol=80 dB
The amount of lead compensation one needs decreases with the higher GBW model, so that's the only change made in the two .asc's attached. I, understandably, pushed the lower GBW model, leaving a lot of loop gain on the table for the higher GBW model, but without knowing what I have, it's *hopefully* a safer bet.
Putting the probe anywhere on the outer loop yields the same result.
Comments/critiques appreciated! I'm here to learn.
Thanks,
Daniel
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Really? I suspect you have not understood me/I haven't made myself clear.
The "outer loop" is not a useful formulation of the problem.
Can you post a plot with the probe where I recommended?
Use the same format as the previous posts with a screenshot of the circuit so as to confirm no miscommunication
Best wishes
David
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I prefer the simple V probe when it works - which is anywhere the reverse conduction is negligible
which would be in a sim when one side is a Vsource 0 Ohm output or a controlled source infinite Ohm input
the simplification of avoiding a stepped analysis for the loop gain then frees up .step for component/parameter stepping to explore the circuit's suspected range of variation
of course actual data on real chips current production center and spread would real good to have - with these older power chip amps they are all old enough to have to have been transferred to newer fabs with tighter tolerances, higher intrinsic performance - they could well be all "above average" relative to their unchanged decades old datasheet params
and a solid design also would want small signal parameter variation with operating point - low idle current to near triggering current protection, likewise for Vsaturation - the MOSFET output chips are a question with major Cds nonlinear jump when VDS drops below Vth
which would be in a sim when one side is a Vsource 0 Ohm output or a controlled source infinite Ohm input
the simplification of avoiding a stepped analysis for the loop gain then frees up .step for component/parameter stepping to explore the circuit's suspected range of variation
of course actual data on real chips current production center and spread would real good to have - with these older power chip amps they are all old enough to have to have been transferred to newer fabs with tighter tolerances, higher intrinsic performance - they could well be all "above average" relative to their unchanged decades old datasheet params
and a solid design also would want small signal parameter variation with operating point - low idle current to near triggering current protection, likewise for Vsaturation - the MOSFET output chips are a question with major Cds nonlinear jump when VDS drops below Vth
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Yes, it certainly works after a V source.
But once there is a real circuit then one needs to think every time whether the simple probe is adequate or whether to move to a better probe.
This is error prone and subject to inconsistency once the circuit finally does need a Tian probe.
I prefer to use the Tian probe everywhere and not risk mistakes where I expected the simple probe to be accurate and it wasn't.
.Step can nest three deep so there is no problem to put even two nested parameter steps with a Tian probe. I have never needed to nest three different parameters AND a Tian probe. Just too cluttered for me to interpret.
So I see no real cost to use the Tian probe as the default.
Yes, I think the TDA model is the key, but I want to have certainty in the simulation first.
Best wishes
David
JCX, David,
Thank you guys for your help so far. I really appreciate it! Agree entirely that having a solid set of measurements for the TDA7293 is very important to squeeze, well, most anything out of these chips.
David,
My mistake on the location of the loop gain probe. I foolishly assumed that injecting on any side of the node would result in the same result, but alas, not the case.
Attached are both suggested loop gain tests, along with the appropriate circuit images (modified the least I could do) of the 8MHz GBW macromodel. First image shows the results of the Tian probe and the second image shows the loop gain via JCX's suggestion (which looks very similar to the Tian probe at the same location).
Thanks,
Daniel
Thank you guys for your help so far. I really appreciate it! Agree entirely that having a solid set of measurements for the TDA7293 is very important to squeeze, well, most anything out of these chips.
David,
My mistake on the location of the loop gain probe. I foolishly assumed that injecting on any side of the node would result in the same result, but alas, not the case.
Attached are both suggested loop gain tests, along with the appropriate circuit images (modified the least I could do) of the 8MHz GBW macromodel. First image shows the results of the Tian probe and the second image shows the loop gain via JCX's suggestion (which looks very similar to the Tian probe at the same location).
Thanks,
Daniel
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No problem. Probe placement is crucial once you try multi-loop schemes so it is important to be correct.
The results now look much more reasonable so we can proceed.
One point is that the TDA model is perfectly minimum phase.
So theoretically there is no limit to how far we can push the ULGF if we correctly cancel the poles with zeroes.
I don't know what the practical limit for this is.
JCX may have some real data on this.
A simple V source probe at this location will match the Tian probe but I don't think it's very useful.
I suspect it's not JCX's recommendation.
Best wishes
David
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I have played in sim with cancelling the excess poles of the shown model - need a >200 MHz op amp since my sim presently has >20dB peaking at 10 MHz in the compensation
not something to casually suggest as a good idea in the real world
the big deal is the power chip amp open loop gain/excess pole uncertainty - hard to find any clue whatsoever on the tda7293 GBW, open loop gain
what is scary for these schemes is the M3886 DS gives 2 MHz min with 8 MHz typ as its GBW - that's already 4:1 range with no clue on how much faster it could be
and if you start cancelling higher order poles then the boost can cause loop instability if your compensation starts to much before the particular chip you are using extra poles kick in
not something to casually suggest as a good idea in the real world
the big deal is the power chip amp open loop gain/excess pole uncertainty - hard to find any clue whatsoever on the tda7293 GBW, open loop gain
what is scary for these schemes is the M3886 DS gives 2 MHz min with 8 MHz typ as its GBW - that's already 4:1 range with no clue on how much faster it could be
and if you start cancelling higher order poles then the boost can cause loop instability if your compensation starts to much before the particular chip you are using extra poles kick in
Thanks, guys. Even the zero from C6 causes healthy peaking over the 2-8 MHz range I "modeled" if left unchanged.
As I (mostly) expected, I'll need to measure the chips I already have on hand before proceeding too much further. I'm at a major research university with an even larger EE department...someone's got to have a nice analog lab around here that I can beg/borrow/steal my way in to. Anyhow, I'll start a different thread for that.
If you have some tips/tricks that I should look at from a learning perspective, I'm all ears. Have a great weekend.
As I (mostly) expected, I'll need to measure the chips I already have on hand before proceeding too much further. I'm at a major research university with an even larger EE department...someone's got to have a nice analog lab around here that I can beg/borrow/steal my way in to. Anyhow, I'll start a different thread for that.
If you have some tips/tricks that I should look at from a learning perspective, I'm all ears. Have a great weekend.
I see the problem as three levels of approximation.
1. Your current minimum phase, specified TDA model.
Question is what compensation and outer amp requirements.
To maintain control of the combined loop behaviour out to about 10 MHz will require the additional op-amp to have useful gain out to 6 to 10 times more. If the additional amp is first order then the GBW is the metric, in the order of 100 MHz. Some op amps are not simple first order and the unity gain frequency as well as the effective order needs to be considered.
2. Minimum phase TDA model but with uncertainty.
Now the question is how to be sure stability is adequate in the face of variability in the TDA.
This is classic control theory. You could look at I. Horowitz and his work on Qualitative Feedback Theory (QFT). He works in frequency domain so it's easier to apply practically, compared to a lot of the control theory literature that is very abstract.
3. Non minimum phase effects in the TDA.
This sets upper limits on the achievable. Bob Cordell's book seems to show some non MP behaviour even for simple EF outputs, even in simulation, but it will need measurement to be sure.
I have seen a few cases where it has started to be noticeable but usually it is only relevant when you push the boundaries.
None the less, it's educational to explore the limits and I would like to understand this better.
Maybe your data will help, are you at UCSD?
Best wishes
David
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