Have a look at my new TDA1545 DAC (lots of details on page)

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Re: Output stage

peufeu said:


Indeed. But tis Vgs can vary at both ends : the opamp controls the gate part, but not the source part. Vs is actually free to move, according to JFET impedance and current through it.

Thus, if a current variation happens, which is too fast for the opamp, Vs will change, hence Vgs will change, hence the JFET will act on its own.

The opamp cannot control the current running through the JFET. This is the principle of a Cascode.

Hm.

Sure, but as soon as Vs moves, that gives an input at the opamp, and the opamp will want to react on it (will move the gate so that Vs returns to zero). So, whichever way you cut it, the opamp is always there doing something.

Jan Didden
 
Hi Peufue,

I agree with Jan, the opamp is still doing something, just it's influence is not as bad as with conventional opamp I/V's.

I started of with the J309 fet with a Gfs of say 10mS

Later I replaced it with a small mosfet BS170, which has a higher Gfs, hence lower dynamic source impedance. The opamp has less correction to do on the mosfet gate now. It sounds better IMHO

Even later I replaced the BS170 with a BC547 transistor. This results in a much lower dynamic impedance, sounds better again. (you can try this very easily in your circuit)

Now make that opamp a DC servo and just listen.:cool:

BTW,
You're right that the I/V conversion resistor is extremely critical in these common gate / common base I/V circuits.
After loads of listening tests I've settled on a parallel combo of 1.8K Riken with 10K DALE RNC65C.
 
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Rudolf,

I think we all are looking for that "ideal" I/V. What interests me in your setup is how the error voltage at the opamp inverting input looks. In the traditional I/V you will see the steps, and these are the most problematic for the opamp. How does that look in your system? I expect them to be lower, but the spectrum probably is the same?

Seondly, have you thought about using one of those high-speed communications opamps that are becomimg available?

Jan Didden
 
IV-Converter

janneman said:
Rudolf,

I think we all are looking for that "ideal" I/V. What interests me in your setup is how the error voltage at the opamp inverting input looks. In the traditional I/V you will see the steps, and these are the most problematic for the opamp. How does that look in your system? I expect them to be lower, but the spectrum probably is the same?

Seondly, have you thought about using one of those high-speed communications opamps that are becomimg available?

Jan Didden

Hi Jan,
You must see the steps when you don't apply low-pass filtering!
My idea is to smooth out the steps by analog low-pass filtering. Can't help the sampling frequency of redbook CD's was chosen that low (44.1kHz), meaning that the filter should start at 20 kHz when it is a steep high order one.
For filtering 192 kHz would be much more ideal, but the DVD-Audio does not seem to make it. SCAD: digital filters again.......
:bawling:
 
Sorry if I didn't make myself clear Jan,

I just gave Pierre some hints to improve the sound, like using transistor and "degrading" the opamp to a DC servo for the DAC output.

I gave up on traditional opamp I/V converters a couple of years ago, with the LM6172 sounding "best" to my ears.

The opamp driving a jfet cascoding the DAC was a nice step forward.
Even then the sound of opamp would creep through :bawling:
Again I prefered LM6172 in this position above OPA2604, OPA2132, AD826 to name a few.

The steps to small mosfet and transistor brought some more improvements, and getting rid of the feedback loop was the next natural thing.

I've been thinking about using a CFP with shunt feedback for the common base transistor to lower the dynamic impedance without having a big bias current.
Measurements so far for a zener referenced CFP emitter follower "regulator" give me some doubts; the HF noise goes down a little bit, but my scoop images become fuzzier, indicating some very high frequency micro oscillations. Could be my "big" physical loop (used a multi-turn potmeter hoping to find the optimum shunt feedback point).

I still like the very simple common base I/V a lot.
I still need to find some time to have new pcb's made for the next version, prepared for CFP, folded cascode for DC coupling and DC servo.
 
rbroer said:
I agree with Jan, the opamp is still doing something, just it's influence is not as bad as with conventional opamp I/V's.

Yes, the opamp has an error voltage and its output moves. My theory was that the DAC output voltage compliance was good enough so that the opamp liimtations would not matter. In light of what you say below, I may have been overoptimistic :

I started of with the J309 ... small mosfet BS170... BC547 transistor. This results in a much lower dynamic impedance, sounds better again. (you can try this very easily in your circuit)
Now make that opamp a DC servo and just listen.:cool:

My hypothesis was that we should have the least possible current flowing through the opamp output into the signal, thus I used a JFET which has low gate current.

However your listening tests seem to prove me wrong as the BJT, with much higher base current, is the best ! What DAC chip are you using ?

For the DC servo, which filter order so you use ? Care to posta schematic ?

BTW,
You're right that the I/V conversion resistor is extremely critical in these common gate / common base I/V circuits.
After loads of listening tests I've settled on a parallel combo of 1.8K Riken with 10K DALE RNC65C. [/B]

I've gotta try some tantalums.
I'll take a snapshot of opamp error voltages, etc. for posting here.

janneman said:
Seondly, have you thought about using one of those high-speed communications opamps that are becomimg available?
Jan Didden [/B]

I used AD825, good compromise between speed and price... also JFET input.

Have to take that digicam out...
 
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Rudolf,

Are you familiar with the CFP based I/V converted published in Audio Amateur (lot of years ago)? If not, I can post a quick sketch, but I think a similar one was posted on this forum already. You enter the current in the emittor of one half of a dual, the other one biased to keep the emitters at zero voltage level.

Jan Didden
 
Back to the digital section...

What i mean is that after the first FF (IC2) you have your I2S signal as in the diagram: ws and data change on bck going low, the dac reads the inputs at bck going high.

So why the extra ff for bck? You just move bck a bit, so it changes after ws and data have changed. But since the dac does nothing at that moment, it should not matter if bck goes low when ws/data change or a bit later.

Good luck with your computer connection. Interesting application.
Mind you that you probably have to divide your clock to match it to a valid i2s clockfreq (divide by eight?).

===

SAA7210 is only decoder, so no oversampling. There is the (in)famous 7220 after the 7210 to do that . I2S inbetween these chips. Insulation is going to be done by fast HP opto-couplers. I already have them (4) and tested them. They are fast enough.

The digital part works fine. For the analog part i am using a opamp i/v convertor for testing. I get 'sound', now i need a decent circuit to get 'music'. As you can see from the reactions here to your circuit, there is a lot to it. I'm just browsing the posts to get a decend circuit. Mind that i have balanced ouput with my two tda's (or not, adjustable).

And also the powersupply is not done yet. Recent months i did not have much time (new house) and my test cd player died. I am waiting on a component to fix it (Elso?).

Regards,
GuidoB
 
rbroer said:
Even then the sound of opamp would creep through

That's why I selected a good sounding opamp... my intuition told me it'd creep through... argh. You tried AD825 ? I can mail 2 to you if you like.

I've been thinking about using a CFP with shunt feedback for the common base transistor to lower the dynamic impedance without having a big bias current.

Care to post a schematic ? I'd like to try another "super-JFET" : a CFP with a JFET and a Bipolar (the Bipolar doing the weight lifting and the JFET having its gate on the Ref voltage).

high frequency micro oscillations

CFPs are picky on layout and will oscillate if the wires between the two transistors are longer than a few cm. Maybe this is it ?

I still like the very simple common base I/V a lot.

Better than with the opamp ?

I still need to find some time to have new pcb's made for the next version, prepared for CFP, folded cascode for DC coupling and DC servo.

I can pay for half the PCBs cost (or help you routing them) as I'm interested in your results. If you want we can make a team.

What DAC chip do you use ? TDA1543 ? Do you use reclocking ?

Regards,
Pierre
 
guido said:
Back to the digital section...

What i mean is that after the first FF (IC2) you have your I2S signal as in the diagram: ws and data change on bck going low, the dac reads the inputs at bck going high.

So why the extra ff for bck? You just move bck a bit, so it changes after ws and data have changed. But since the dac does nothing at that moment, it should not matter if bck goes low when ws/data change or a bit later.


You are right, it shouldn't matter... maybe it was just paranoid-ness from me.

But I still wanted to reclock BCK twice, because I did not want to feed a jittery signal to the BCK reclocker in fear of feeding noise into it at the same time.

Good luck with your computer connection. Interesting application.
Mind you that you probably have to divide your clock to match it to a valid i2s clockfreq (divide by eight?).

Yes, I would have to divide the clock freq and send it to a SPDIF encoder to give a good SPDIF signal to the soundcard.

===

SAA7210 is only decoder, so no oversampling. There is the (in)famous 7220 after the 7210 to do that . I2S inbetween these chips. Insulation is going to be done by fast HP opto-couplers. I already have them (4) and tested them. They are fast enough.
[/QUOTE]

Good !

Balanced output ? Want to use some transformers ?
DON't make your audio run through current mirrors. I tried, it sucked.
 
IV-Converter

janneman said:
Rudolf,

Are you familiar with the CFP based I/V converted published in Audio Amateur (lot of years ago)? If not, I can post a quick sketch, but I think a similar one was posted on this forum already. You enter the current in the emittor of one half of a dual, the other one biased to keep the emitters at zero voltage level.

Jan Didden

Hi Jan,
The circuit I posted is a fusion between yours, Rudolfs and Jocko's.
I did not build it yet.
;) ;)

http://www.diyaudio.com/forums/showthread.php?postid=201512#post201512
 
I want to try your output stage!

Peufeu,

If you read the 'Simple I-V stage' thread you will find I have been enquiring about discrete I-V conversion that will operate at +/- 5 (five) Volts with my AD1865N-K. I would really like to try as many methods as possible and the final schematic on your website looks ideal for my purposes.

I intend to set R1 at 3K. Since the Ad1865N-K outputs 1mA, this will provide me with a nice 3V signal.

What values of resistor would seem appropriate for R2 and R3?
Note: I am using Nicad supply, therefore not too much current! BTW approx what current will your circuit draw?

I have some J309s and J310s- which ones are best in each location?

Finally, how can I calculate C1 for a given cutoff frequency?
(f=1/(2xpixRxC)?

Lots of questions, but I am keen to give it a try!
 
what is the typical rise time of the steps coming out of the DAC? I mean, normally this is (digitally) filtered, no

Well Jan, I don't know.
I assume it depends on the DAC itself and on the I/V being used.
The current out/in will be staircased anyway, worst case scenario in a non-oversampling case is a full scale step.
I assume in applications with oversampling and digital filtering the step sizes will be lower on average statistically, but I may be skating on thin ice now :)

I think ELSO sent me a copy of the cfp circuit you mentioned.

Regards,
 
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