Has anyone seen this front-end before?

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Oh dear. This is getting more embarrassing! :eek:

In preparing my answer to you I began to wonder why I referred to the new scheme (with the additional cap) as "three pole". Look at the response curve: I can only see two poles and one zero, where's the alleged extra pole and zero? Well, as it turns out, if you place the additional cap in series with the resistor, the impedance of the resistor-capacitor combination does indeed now have a pole and a zero. However, when substituted into the expression for rm, you end up with a new pole and zero both at DC - i.e., they cancel and what you're left with is still a two-pole response but you now have much more control over the pole frequencies.

Taking C large (in the order of 1 uF) will give you a mostly unchanged response (i.e. the poles are complex). As you decrease C, this damps the poles and eventually splits them into two real poles and moves them further apart in frequency, as shown in figure 15 of the paper. Decreasing C further will take you closer and closer to the single-pole response.

With Bob's "bridged T" approach you can achieve the same effect, however here taking C large takes you closer to a single-pole response and taking C small takes you closer to the original two-pole response with complex poles. With the bridged-T approach, if all you want to do is damp the poles but keep them close together in frequency (in order to maximise loop gain) you will find you need a very small capacitance (in the order of units of pF).
 
“A General Relationship Between Amplifier Parameters, And Its Application to PSRR Improvement” E Sackinger, J Groette, W Guggenbuhl, IEEE Trans CAS vol 38, #10 10/83 pp 1171-1181

I forgot to say thank you for posting this. I had been under the impression that an op-amp with no ground connection (i.e. all of them) was limited to PSRR being equal to loop gain, and had not appreciated that there was actually a CMRR:pSRR tradeoff. This is presumably because all the opamps whose datasheets I've studied closely were ones that choose to maximise CMRR.

Anyway, I have often wondered why single op-amps don't have a ground connection. The vast majority have at least one n/c pin so it's not like it's a packaging limitation. Any ideas? Perhaps most designers don't feel a very high PSRR is necessary as this can easily be mitigated externally by using properly regulated and decoupled power supplies, so they maximise CMRR and leave the circuit designer to deal with the PSRR issue.

… I began to wonder why I referred to the new scheme (with the additional cap) as "three pole". Look at the response curve: I can only see two poles and one zero, where's the alleged extra pole and zero? Well, as it turns out, if you place the additional cap in series with the resistor, the impedance of the resistor-capacitor combination does indeed now have a pole and a zero. However, when substituted into the expression for rm, you end up with a new pole and zero both at DC - i.e., they cancel and what you're left with is still a two-pole response but you now have much more control over the pole frequencies.

Given that "three pole" is clearly a misnomer, this approach needs a new name. How about "split two-pole" compensation?
 
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yes I've commented on the high sensitivity of bridging the "T" with a C as Bob suggested

for a single Q VAS its internal Ccb will be significant

you would need Cascode or "beta enhanced" VAS to see really high 2-pole Q in practice

Hi jcx,

I somehow missed your comments on the sensitivity of the bridged T compensation technique I suggested (or I just forgot, as happens all too often). Could you point me to those comments?

I must admit that I have never tried Bridged T compensation with a single-transistor VAS. As you know, I do not advocate such a VAS. I have trouble understanding why anyone would want to apply advanced compensation techniques to such an inferior VAS. More importantly, however, I'm very interested to know about problems that may exist with the use of the Bridged T compensation technique with 2-transistor VAS designs where Ccb is blocked.

Cheers,
Bob
 
I somehow missed your comments on the sensitivity of the bridged T compensation technique I suggested (or I just forgot, as happens all too often). Could you point me to those comments?

I must admit that I have never tried Bridged T compensation with a single-transistor VAS. As you know, I do not advocate such a VAS. I have trouble understanding why anyone would want to apply advanced compensation techniques to such an inferior VAS. More importantly, however, I'm very interested to know about problems that may exist with the use of the Bridged T compensation technique with 2-transistor VAS designs where Ccb is blocked.

Cheers,
Bob

Hi Bob,

I believe jcx was addressing two separate issues in his post:

Firstly, the fact that the bridged-T is highly sensitive to the value of the bridging cap, if you wish to maintain the two poles close together. (this sensitivity is independent of VAS configuration).

Secondly, was suggesting a possibility why the Q of the complex poles is substantially over-predicted when using the very simple VAS analytical model from my AES convention paper. Certainly that model is assuming a "perfect" transistor with constant beta and ignoring any parasitics such as Ccb. So, I believe that jcx may be suggesting that it could be the omission of these parasitics from my model that results in the difference between predicted Q and simulated Q.

However, the simulated Q was in fact from an amplifier using a beta-enhanced VAS (although without a cascode). Presumably this means that other assumptions made in the simple model are contributing to the over-prediction of Q - such as the model assuming perfect transimpedance operation for all frequencies from DC.
 
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Hello Dave,

Certainly the Q of the poles is something that puts some people off TPC. As noted in my paper, you can introduce a further pole zero pair by adding a capacitor in series with the TPC resistor. If the loop gain poles have a high Q, by selecting the appropriate additional capacitor value, you can make the loop gain look like it just has two critically damped poles (plus the zero at higher frequency) rather than three poles and two zeros.

Well, that's my take on it and I look forward to further discussion!

Hello HarryDymond if i understand this; to me this is making a floating net, ie a star connection of 3 caps of different value. This net without anny potensial reference(?), capasitor voltage build up/down. Som spice program may allert/warn or wont sim?:h_ache:
A solution may bee to convert star to delta and ommit the floating net. The result is a combination of two stabilisation tecniques? wich already has names or have i missunderstud somthing essensially here ?
 
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Hello HarryDymond if i understand this; to me this is making a floating net, ie a star connection of 3 caps of different value. This net without anny potensial reference(?), capasitor voltage build up/down. Som spice program may allert/warn or wont sim?:h_ache:
A solution may bee to convert star to delta and ommit the floating net. The result is a combination of two stabilisation tecniques? wich already has names or have i missunderstud somthing essensially here ?

I understand your concern, but at DC, my proposed "split two pole" compensation looks exactly the same as "standard" miller compensation. If your simulator can cope with that (and if it can't you've either made a mistake or should get a new simulator!), it should be able to compute a DC operating point for a circuit employing split two pole compensation. If there is an issue it may be solved by placing a large (1 Gohm) resistor in parallel with the additional cap.

It is possible that in a real-life circuit, the amplifier will take a while (a couple of seconds) to find a stable DC operating point (I'm not sure that split two pole compensation makes this any better or worse), sticking to one of the power rails before settling. Most amps overcome this by disconnecting the output from the speaker terminals with a relay and only closing the relay after the start-up transient is over and low DC offset is verified.

I have built several amplifiers (and simmed a lot more) using the split two pole compensation technique without problems.
 
Fortunately, the main insights delivered - the ULGF frequency, zero frequency, current requirements of the VAS/TIS and input stage, that the large and small caps should have their positions reversed relative to the suggestions of Self and Slone, and the fact that the value of R1 only has an effect on the loading of the input stage and a higher value makes the loading worse - are all valid
And valuable to publish because somewhat counter intuitive. Thank you.
The proposed method of simulating loop gain doesn't work above the ULGF or at very low frequencies (<5 Hz) :eek::eek::( (note this means it cannot be used to predict gain margin). However, for 5 < f < ULGF, the method does work better (gives more accurate results) than the "break loop and insert great big inductor" method and can be used to observe the "correct" behaviour of the poles, the zero, the ULGF and the phase margin. This has been verified by comparing the method to the only proper way to simulate loop gain: with the General Feedback Theorem, or a close second, with Tian's method. Sadly I had never heard of Middlebrook or Tian at the time I wrote the paper.
I was just about to compare the consistency of your method and Tian. You have saved me much work! And thanks for the reference. Very helpful summary.
Certainly the Q of the poles is something that puts some people off TPC. As noted in my paper, you can introduce a further pole zero pair by adding a capacitor in series with the TPC resistor. If the loop gain poles have a high Q, by selecting the appropriate additional capacitor value, you can make the loop gain look like it just has two critically damped poles (plus the zero at higher frequency) rather than three poles and two zeros.

Finally, it bears emphasising that the frequency and Q of the loop gain poles are very sensitive to VAS/TIS transistor beta (and also sensitive to output stage beta) and will therefore vary dramatically from one instance of an amplifier to another.

The Q of the poles is actually what attracts me to TPC. My idea is to approach closer to Bode maximum feedback and moderate Q poles are helpful for this. Hence my queries on Q prediction and control.
Since Bode maximum feedback uses an irrational function that is analytically awkward, it will be easiest to approximate it by trial and error simulation anyway. So some inaccuracy in your model is not of concern now I know it was not my error. But extreme sensitivity to a poorly controlled parameter like Beta is not helpful. Need to study this.

Best wishes
David
 
I have trouble understanding why anyone would want to apply advanced compensation techniques to such an inferior VAS.
You are not alone!
More importantly, however, I'm very interested to know about problems that may exist with the use of the Bridged T compensation technique with 2-transistor VAS designs where Ccb is blocked.

Cheers,
Bob

Do you have any comments on your BTPC versus Harry Dymond's Split TPC?
If they are more or less equivalent perhaps we need a collective name for TPC with Q control - QTPC?;)
And what happens when we combine them?

Best wishes
David
 
I have added an addendum to my AES two-pole compensation paper. The link is still the same. The majority of the addendum is based heavily on what I've written in this thread but those who have downloaded the previous version may wish to re-download so all the information is contained in one place. I will get in touch with the AES to discuss the possibility of getting the updated version into their online library.

Thank you to everyone here for raising questions about the paper and helping me to appreciate some of the finer details.
 
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Hi jcx,

I somehow missed your comments on the sensitivity of the bridged T compensation technique I suggested (or I just forgot, as happens all too often). Could you point me to those comments?

I must admit that I have never tried Bridged T compensation with a single-transistor VAS. As you know, I do not advocate such a VAS. I have trouble understanding why anyone would want to apply advanced compensation techniques to such an inferior VAS. More importantly, however, I'm very interested to know about problems that may exist with the use of the Bridged T compensation technique with 2-transistor VAS designs where Ccb is blocked.

Cheers,
Bob

Hi Bob,
I use Brdged T compensation(together with local VAS NFB) in mine TT amp and it works quite good with no oscilation and the sound is very good. I used 1.2pF to 2.2pF for the bridge capacitor. It is buffered VAS(2-transistor). I would appreciate your comment. I learned a lot from your book specilly about thermal compensation.
Here is a link:http://www.diyaudio.com/forums/solid-state/182554-thermaltrak-tmc-amp-10.html#post3031504
Damir
 
Hi

I notice Shinichi Kamijo died at 28th march.
His website will be removed at the end of June.
We should download his great works and save it in own PC.

Thank you for informing us. Shinichi Kamijo was really an innovative and very productive designer.
I just copied his complete website using HTTrack website copier (HTTrack Website Copier - Free Software Offline Browser (GNU GPL)). It took 52 minutes to copy 2560 files, after scanning 2669 links. The difference is mainly due to some dead links.

Steven
 
Hi
I notice Shinichi Kamijo died at 28th march.
His website will be removed at the end of June.
We should download his great works and save it in own PC.

Although I've never heard of this guy. I would say RIP.

Not due to you Edmond old chap...
This front end has been done before by Shinichi Kamijo here:

Evolve Power Amplifiers

Great!
Please, provide a link to the schematic.



Which 'stupid remark' have i made you ignorant fool?
This one:
This front end that you call yours is in fact due to a japanese designer, and can't be compensated by minor loop means such as two pole so-called TMC or ordinary Miller compensation.
So please, stop misleading the ignorant and ill-informed with your nonsense.
Waly is right about you.
:(
And this one:
Miller compensation, be it two pole or TMC, is not possible because the second stage does not phase invert. One, alas, is left with shunt compensation to ground from the output of the second stage.

Oh, really?
BTW, perhaps you don't know it, but the inverting input of the IPS does invert the phase. :p


[..]
what Edmond would have us beleive are his circuits are invariably nothing of the sort: he simply obtains them from the web and elsewhere and pretends to have come up with them independently.:(

1. As said already, never heard of Shinichi Kamijo, let alone I would have copied his front-end.
2. Apart from a complementary/symmetrical geometry and MIC, Shinichi Kamijo's front-end is different in all other respects.
3. Regarding specific circuit details, I gave credits where credits needed to be credited, except in one case, about MIC, which I totally forgot to mention. Admittedly, that was a serious omission. But here it is anyway: "MOSFET Compensation", Letters to the editor, Electronics World, Oct. 2002, p. 29, by...... (guess who!) :p

Cheers,
E.
 
Welcome back Edmond,

Thanks, Alex.

We spent our vacation in a nice apartment at the Cote d'Azur with this panoramic view (stitched from four photo's).

I was starting to think I am going blind as I could figure out how Kamijo's front end was the same.

Don't worry; clearly it's someone else who is stone-blind and doesn't understand the schematics. ;)

Cheers,
E.
 
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