Yes, a hint on how things are coming would be greatly appreciated...
I am seriously torn between getting an Opus or COD now, before this run runs out, or waiting for the Buffalo...
Decisions... decisions...
PS, [shameless plug mode] will beta test, build bare boards, offer lab testing, etc... [/shameless plug mode]
I am seriously torn between getting an Opus or COD now, before this run runs out, or waiting for the Buffalo...
Decisions... decisions...
PS, [shameless plug mode] will beta test, build bare boards, offer lab testing, etc... [/shameless plug mode]
DAC jitter reduction and quality of chips
About the jitter reduction abilities of the ESS Sabre DAC:
As I understand it the Sabre DAC reduce input jitter effectively, but just to make sure: Does that mean that I can use a non high-end SPDIF source with a mediocre clock and still get high-end performance in the end, or is the jitter reduction something intrinsic to the DAC chip after all?
Another issue, the Sabre DAC seems to be available in three levels of quality: Reference, Ultra, and Premier. What are the differences here and what quality level are you guys aiming for for the DAC board production?
Regards,
Dex
About the jitter reduction abilities of the ESS Sabre DAC:
As I understand it the Sabre DAC reduce input jitter effectively, but just to make sure: Does that mean that I can use a non high-end SPDIF source with a mediocre clock and still get high-end performance in the end, or is the jitter reduction something intrinsic to the DAC chip after all?
Another issue, the Sabre DAC seems to be available in three levels of quality: Reference, Ultra, and Premier. What are the differences here and what quality level are you guys aiming for for the DAC board production?
Regards,
Dex
Re: DAC jitter reduction and quality of chips
Hi Dex,
In order to get good performance, you need 1 good clock, that being the one connected to the XIN/XOUT pad. You may put in a seriously degraded spdif signal, one thats so bad that some SPDIF to I2S chips wont even lock and still get the good performance. That being said, even when using a "not so good" clock for XIN/XOUT, I have compared the Sabre to other DAC's (not allowed to say names, but you guys know them very well) and when using these clocks, the performancve is still superior when the transport clock (I2S or SPDIF) has the most jitter. In the event the transport is excellent, and you use a mediocre clock for the XIN/XOUT, then the performance was still slightly better.
Hope this answers the first question.
Sabre Refference 64 pin TQFP 132 DNR, 115 THD+N
Sabre Ultra 48 pin QFN 128 DNR, 115 THD+N
Sabre Premier 48 pin QFN 126 DNR, 115 THD+N
Sabre Refference and Ultra both have -120dB of image rejection in the oversampling filter.
Sabre Premier has 60dB image rejection.
Numbers are when configured in stereo mode
I have had board exceed these performance levels, just not "easy to get" You have to hand select the opamps, and even caps sometimes.
Dustin
DexterMorgan said:
Hi Dex,
In order to get good performance, you need 1 good clock, that being the one connected to the XIN/XOUT pad. You may put in a seriously degraded spdif signal, one thats so bad that some SPDIF to I2S chips wont even lock and still get the good performance. That being said, even when using a "not so good" clock for XIN/XOUT, I have compared the Sabre to other DAC's (not allowed to say names, but you guys know them very well) and when using these clocks, the performancve is still superior when the transport clock (I2S or SPDIF) has the most jitter. In the event the transport is excellent, and you use a mediocre clock for the XIN/XOUT, then the performance was still slightly better.
Hope this answers the first question.
Sabre Refference 64 pin TQFP 132 DNR, 115 THD+N
Sabre Ultra 48 pin QFN 128 DNR, 115 THD+N
Sabre Premier 48 pin QFN 126 DNR, 115 THD+N
Sabre Refference and Ultra both have -120dB of image rejection in the oversampling filter.
Sabre Premier has 60dB image rejection.
Numbers are when configured in stereo mode
I have had board exceed these performance levels, just not "easy to get" You have to hand select the opamps, and even caps sometimes.
Dustin
A/D converter advice...
Hi Sabre DAC people,
Anybody here who knows about a superb sounding A/D converter ... e.g. 20-24 bit at e.g. 400 kHz sampling frequency (or, if not possible at 192 kHz) w/o internal filters, oversampling or digital conversions?
Or a low-order (e.g. second or third order) delta-sigma A/D converter capable of operating at 11,289 MHz and with a "straigthforward"/standardized output? Again without internal conversions of any kind...
I'm looking for a design having the potential for outstanding sound - not necessarily the best possible data.
Suggestions are appreciated
Jesper
Hi Sabre DAC people,
Anybody here who knows about a superb sounding A/D converter ... e.g. 20-24 bit at e.g. 400 kHz sampling frequency (or, if not possible at 192 kHz) w/o internal filters, oversampling or digital conversions?
Or a low-order (e.g. second or third order) delta-sigma A/D converter capable of operating at 11,289 MHz and with a "straigthforward"/standardized output? Again without internal conversions of any kind...
I'm looking for a design having the potential for outstanding sound - not necessarily the best possible data.
Suggestions are appreciated
Jesper
Spartacus said:
This is a tough question an answer, and many people carry vstly differing opinions on this subject. All I can say is what I use as the methodology when designing the DAC.
1. Most important in this design was immunity to jitter coming from the input transpart, whatever it was.
2. Then I tried to keep the responce to be "linear phase" so that the group delay was constant.
3. Use enough bits in each part of the chain such that the quantization error was not enough to cause degredation of DNR at final output.
4. Use simple Dynamic element matching algorythm, i.e dont make anything more complicated than it needs to be.
5. I know its last, buts its the one I spent most of the time on, so this one should really be first, do a damn good job of matching EVERYTHING, even parasitics in the analog section of the chip.
I hope that answers it
Re: I know this is a DAC thread but...
Probably worth starting a new thread.
Currently the best ADC's chips are from AKM (123dB DR / 110dB
THD) Cirrus (120dB DR / 110dB THD) TI (124dB DR / 108dB THD.
All pro audio ADC's that are exceeding this are using gain ranging
IP architectures for example Lavry Engineering, Stage tech, Prism
etc.
I believe current lowest distortion ADC is discrete 1 bit design by
Bruno Putzeys (and others), see grimmaudio. It is a DSD ADC and
requires DSD -> PCM conversion, but appears to be as good as it
gets linearity wise. DR is similar to chips.
I'm not sure what is used in the Dcs ADC.
Do some searching and you will find all this.
cheers
Terry
gentlevoice said:
Probably worth starting a new thread.
Currently the best ADC's chips are from AKM (123dB DR / 110dB
THD) Cirrus (120dB DR / 110dB THD) TI (124dB DR / 108dB THD.
All pro audio ADC's that are exceeding this are using gain ranging
IP architectures for example Lavry Engineering, Stage tech, Prism
etc.
I believe current lowest distortion ADC is discrete 1 bit design by
Bruno Putzeys (and others), see grimmaudio. It is a DSD ADC and
requires DSD -> PCM conversion, but appears to be as good as it
gets linearity wise. DR is similar to chips.
I'm not sure what is used in the Dcs ADC.
Do some searching and you will find all this.
cheers
Terry
Hi terry, Dustin & Brian
Thanks for your comments & suggestions
Yes, I know that I am intervening in a thread that has another purpose. As I wrote I hoped that somebody - in an otherwise very interesting and high quality DAC thread (flattering ;-)) - would know about ADCs.
And Terry thanks for your comments - I will look at it.
I look forward to seeing the progress of your endeavors.
Regards,
Jesper
Thanks for your comments & suggestions
Yes, I know that I am intervening in a thread that has another purpose. As I wrote I hoped that somebody - in an otherwise very interesting and high quality DAC thread (flattering ;-)) - would know about ADCs.
And Terry thanks for your comments - I will look at it.
I look forward to seeing the progress of your endeavors.
Regards,
Jesper
Sabre Chip
It's been a while since I've delurked, however this has my attention! I am looking forward to the Buffalo boards.
Qs for Dusty:
a: Do the internals of the Sabre chip clock off rising and falling edges of Xti; or just the rising edge? ie, which edges matter?
2: About the internal analog stage thermal signature: what load minimizes the chip thermal shifts with signal swings? It is likely a parabolic function, but there may be a sweet spot, a particular resistive load, that will minimize internal thermal tails. It will not nesc be the minima for DNR or SFDR, but it may sound good. I'm guessing something like 550 to 650 ohms across the differential outputs in stereo mode. Current out mode is not nesc the sweet spot.
In regards to "thermal tails", I mean in the broader sense: active devices, including pure digital applications will have shifting threshold voltages with thermal shifts, and a chip is awash in isothermal fronts or waves "sloshing"around...the time constants correlate with audible frequencies, typically 1 to 10 kHz depending on chip geometry. This is a recipie for a PWM heater, with time constants of audible consequences for small but significant time and amplitude shifts.
I will have fun fine tuning when I have the HW in hand.
Cheers,
WMS
It's been a while since I've delurked, however this has my attention! I am looking forward to the Buffalo boards.
Qs for Dusty:
a: Do the internals of the Sabre chip clock off rising and falling edges of Xti; or just the rising edge? ie, which edges matter?
2: About the internal analog stage thermal signature: what load minimizes the chip thermal shifts with signal swings? It is likely a parabolic function, but there may be a sweet spot, a particular resistive load, that will minimize internal thermal tails. It will not nesc be the minima for DNR or SFDR, but it may sound good. I'm guessing something like 550 to 650 ohms across the differential outputs in stereo mode. Current out mode is not nesc the sweet spot.
In regards to "thermal tails", I mean in the broader sense: active devices, including pure digital applications will have shifting threshold voltages with thermal shifts, and a chip is awash in isothermal fronts or waves "sloshing"around...the time constants correlate with audible frequencies, typically 1 to 10 kHz depending on chip geometry. This is a recipie for a PWM heater, with time constants of audible consequences for small but significant time and amplitude shifts.
I will have fun fine tuning when I have the HW in hand.
Cheers,
WMS
Re: Sabre Chip
WMS,
In the absence of Dustin, I would hazard an educated guess and
say that 0 ohm dac OP load is optimal for THD -and- thermally
related distortion.
AFAIK, most DEM coding schemes equalize bit share time and
therefore thermal shifts of junctions, but only if the OP currents are
always the same when on.
Once the OP is allowed to voltage swing, an 'on' dac bit will not
necessarily have the same current all the time depending where the
OP voltage is.
Having said the above this dac must have a pretty smart dem coding
scheme as specs with max recommended OP voltage swing are
still super linear.
cheers
T
wildmonkeysects said:
WMS,
In the absence of Dustin, I would hazard an educated guess and
say that 0 ohm dac OP load is optimal for THD -and- thermally
related distortion.
AFAIK, most DEM coding schemes equalize bit share time and
therefore thermal shifts of junctions, but only if the OP currents are
always the same when on.
Once the OP is allowed to voltage swing, an 'on' dac bit will not
necessarily have the same current all the time depending where the
OP voltage is.
Having said the above this dac must have a pretty smart dem coding
scheme as specs with max recommended OP voltage swing are
still super linear.
cheers
T
Hello,
I wonder if the offer for samples is still up ?
I resurrected the Ethernet DAC project after a long pause, and plan to have a massive DAC shootout in 2-3 months, time to build everything. I would like to include this one since it looks very promising. Project includes low jitter, oversampling in the FPGA, etc.
I wonder if the offer for samples is still up ?
I resurrected the Ethernet DAC project after a long pause, and plan to have a massive DAC shootout in 2-3 months, time to build everything. I would like to include this one since it looks very promising. Project includes low jitter, oversampling in the FPGA, etc.
Buffallo Update
Thanks to Brian, I have in my hands a built up Buffalo prototype. The boards took longer than expected because the PCB house made a mistake and they had to be redone. But they are here now and look good.
I have not had a chance yet to listen to it (just got it last night), and I found some firmware changes I need to make before it will work. But perhaps tonight it will be playing music. A brief examination electrically seems to checkout.
I will post some pics soon.
Cheers!
Russ
Thanks to Brian, I have in my hands a built up Buffalo prototype. The boards took longer than expected because the PCB house made a mistake and they had to be redone. But they are here now and look good.
I have not had a chance yet to listen to it (just got it last night), and I found some firmware changes I need to make before it will work. But perhaps tonight it will be playing music. A brief examination electrically seems to checkout.
I will post some pics soon.
Cheers!
Russ