I think the point was if you want other people to look at your design and help, it will be easier for them to see images posted on the thread rather than have to load up a program to see what you have done.
Once you have got them interested with the images they might then be willing to open up the program
Hi Zarandok,
Indeed that's much better to look at.
The few comments I have remain similar, the resistors on the IIS input lines are to be removed - all termination is to be done at source end, not receiver end.
The clock line is a little long (not a major issue but every millimeter helps. I see you have about 5-7mm (?), for local clocks such as this you may want to shoot for 1-2mm max if possible. This will mean the parts on top layer will need to be moved around a bit.
Using vias on power lines is always a good idea, as the inductance offers a measure of isolation and filtering. Try and replicate on both channels if possible, to keep performance as close as possible.
Your analog output seems to be consuming bulk of the space around and close to the chip at the moment, this set of tracks/outputs may need to be rejigged.
Is there a reason for using the SCK on the input connector, or is it just an option? I see it as adding redundant connections and anyway you don't want vias in the clock line. This is why ESS put the clock on the other side of the chip, trying to get it to route neatly is a nightmare and probably not worth the effort. Anyway it probably doesn't need SCK, I would drop it totally.
Finally to the supplies, my head is hurting a little bit as it's late, will take a longer look and see what could be done to reduce the criss-crossing - even if not totally avoidable due to the pin layout. These chips probably need separate left and right supplies anyway, but it could probably work with one set of supplies.
Indeed that's much better to look at.
The few comments I have remain similar, the resistors on the IIS input lines are to be removed - all termination is to be done at source end, not receiver end.
The clock line is a little long (not a major issue but every millimeter helps. I see you have about 5-7mm (?), for local clocks such as this you may want to shoot for 1-2mm max if possible. This will mean the parts on top layer will need to be moved around a bit.
Using vias on power lines is always a good idea, as the inductance offers a measure of isolation and filtering. Try and replicate on both channels if possible, to keep performance as close as possible.
Your analog output seems to be consuming bulk of the space around and close to the chip at the moment, this set of tracks/outputs may need to be rejigged.
Is there a reason for using the SCK on the input connector, or is it just an option? I see it as adding redundant connections and anyway you don't want vias in the clock line. This is why ESS put the clock on the other side of the chip, trying to get it to route neatly is a nightmare and probably not worth the effort. Anyway it probably doesn't need SCK, I would drop it totally.
Finally to the supplies, my head is hurting a little bit as it's late, will take a longer look and see what could be done to reduce the criss-crossing - even if not totally avoidable due to the pin layout. These chips probably need separate left and right supplies anyway, but it could probably work with one set of supplies.
"the resistors on the IIS input lines are to be removed"
- They are NOT to remove, they prevent overshooting of the digital I2S square waves!
"...all termination is to be done at source end, not receiver end."
- I don`t know what does it mean!
- Clock line could be made a little shorter. Have you experience what does it mean 1-2mm + / - line in the sound quality?
- Symmetrical vias are good idea...
"Your analog output seems to be consuming bulk of the space around and close to the chip at the moment, this set of tracks/outputs may need to be rejigged."
- What do you mean exactly? To make the traces wider?
- The SCK on the input connector is an option if I do not want build in an own clock and use the DAC with external SCK coming from the receiver (e.g. USBStreamer). Vias are not good in this line but what can I do else...?
I will try it first w/o extra clock...
- The PSU lines are a little criss-cross... I didn`t have a better idea to make them. The two shunts are not absolutely necessary, one of them can be bridged, but I will have this option (place is enough there).
- They are NOT to remove, they prevent overshooting of the digital I2S square waves!
"...all termination is to be done at source end, not receiver end."
- I don`t know what does it mean!
- Clock line could be made a little shorter. Have you experience what does it mean 1-2mm + / - line in the sound quality?
- Symmetrical vias are good idea...
"Your analog output seems to be consuming bulk of the space around and close to the chip at the moment, this set of tracks/outputs may need to be rejigged."
- What do you mean exactly? To make the traces wider?
- The SCK on the input connector is an option if I do not want build in an own clock and use the DAC with external SCK coming from the receiver (e.g. USBStreamer). Vias are not good in this line but what can I do else...?
I will try it first w/o extra clock...
- The PSU lines are a little criss-cross... I didn`t have a better idea to make them. The two shunts are not absolutely necessary, one of them can be bridged, but I will have this option (place is enough there).
Last edited:
Two questions regarding clock:
- why does somebody build a resistor seriel in the clock line (like in picture)?
- I am considering to remove the SCK line with vias to the I2S connector and will try to make a U.FL (mini coax) smd connector placed by the clock pattern, as alternative. Is it a good idea? Should I change all the I2S connectors to U.FL or leave them as normal pin header anyway?
- why does somebody build a resistor seriel in the clock line (like in picture)?
- I am considering to remove the SCK line with vias to the I2S connector and will try to make a U.FL (mini coax) smd connector placed by the clock pattern, as alternative. Is it a good idea? Should I change all the I2S connectors to U.FL or leave them as normal pin header anyway?
Attachments
Thanks for the remarks, but it is not my DAC.
https://hifiduino.wordpress.com/2013/02/19/es9018-dac-end-r-fully-assembled-dac/
https://hifiduino.wordpress.com/2013/02/19/es9018-dac-end-r-fully-assembled-dac/
Hi Zarandok,
Your multi-channel DAC looks good. I like the PCB layout.
Is there any chance having u.fl connectors for clocks and other signal inputs to get better SI? Is there any possible having a jumper to switch between local async MCLK and external sync MCLK?
Regards,
Ian
Hi Ian, thanks!
My question was just the same: does it make sense to use u.fl connectors at the i2s input? I'll connect the DAC with USBStreamer or nanoSHARC, they have only pin headers (so I need then a coax cable: u.fl -> 2 pins )...
To place a removable (?) jumper in the SCK line is not a wise decision because of very high freq. (>10Mhz). What I have made an u.fl connector pattern under the clock, so you can choose which one you want to use (see pic). But all two together with the possibility of rapid switching between them is hard to realize I think...
But ideas are welcome!
My question was just the same: does it make sense to use u.fl connectors at the i2s input? I'll connect the DAC with USBStreamer or nanoSHARC, they have only pin headers (so I need then a coax cable: u.fl -> 2 pins )...
To place a removable (?) jumper in the SCK line is not a wise decision because of very high freq. (>10Mhz). What I have made an u.fl connector pattern under the clock, so you can choose which one you want to use (see pic). But all two together with the possibility of rapid switching between them is hard to realize I think...
But ideas are welcome!
Attachments
Last edited:
Hi Ian, thanks!
My question was just the same: does it make sense to use u.fl connectors at the i2s input? I'll connect the DAC with USBStreamer or nanoSHARC, they have only pin headers (so I need then a coax cable: u.fl -> 2 pins )...
To place a removable (?) jumper in the SCK line is not a wise decision because of very high freq. (>10Mhz). What I have made an u.fl connector pattern under the clock, so you can choose which one you want to use (see pic). But all two together with the possibility of rapid switching between them is hard to realize I think...
But ideas are welcome!
Hi Zarandok,
Signal integrity is something that has to be taken into consideration if you want to design a high end DAC. It really makes difference if you care about jitter and higher Fs signals.
http://cp.literature.agilent.com/litweb/pdf/5988-5978EN.pdf
If you really have to stick with pin headers, I would suggest you placing u.fl footprints beside that header to make high quality coaxial u.fl cables as an option.
Regarding to the MCLK, what I meant the 'switch between' was the function. The jumper can be used just for enable/disable the local XO. It doesn't have to be placed into the clock path.
twistedpear realized this issue recently, here is their new design:
The Buffalo-IIISE (Stereo Edition) 2-Channel DAC
Good luck to your project.
Regards,
Ian
Thanks a lot!!
I was thinking about how to disable the clock and come the idea that simple unpower it. Than I read the TPaudio manual an it recommends just the same...
I will design it similar like Buffalo III.
That's great!
Happy Xmas!
Ian
Yes, since this DAC is targeting multi-channel features, I expect it can work very well with my multi-channel I2S/DSD FIFO solution.
Ian
Any idea where to get an ES9016 IC from?
Are these chips OK or only fakes??
https://www.aliexpress.com/item/1-P...2754163496.html?spm=2114.40010308.4.19.6Ytbl2
Are these chips OK or only fakes??
https://www.aliexpress.com/item/1-P...2754163496.html?spm=2114.40010308.4.19.6Ytbl2
Last edited:
- Status
- This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.