classd4sure said:
and what triggers your gate drivers?
classd4sure said:
application specific as in "controlling deadtime"? the driver is clearly not designed to specifically address that application, right?
or maybe you should define "application specific" for us before we can have an indepth discussion on that "applicatin specific" means.
classd4sure said:So aside from that there's no application specific devices in electronics hmm... funny
not really.
I'm not an IC driver guru, but there are some that claim to have a handle on deadtime... I doubt it.
Independant high/low side drivers are there to give you a handle on the matter. Given standard component variation (even amongst the same type), it's cool to have a little pot for fine tuning, if that's built in already kind of like it is for the UcD discrete modulator( with current driven bjt's as drivers), but otherwise you're likely in need of an additional adjustable delay circuit.
Leaving it in the hands of a driver IC won't get you too far.
You mentioned "overshoot control", which I think you meant shoot through control, since we're on the topic of deadtime and all, and said you'd leave it up to the driver!
Didn't you swap a bunch of drivers this morning.. looking for one with better sound? That's not design, you select your driver based on your requirements and design the support circuitry around it, including dead time control. If it doesn't have independant hi/low drivers, then you put the delay circuitry after it. To the best of my knowledge there isn't yet a driver IC that will do the job for you, as you said, "leave it up to the driver", won't work very well, as you found out today. Some drivers feature adaptive or predictive deadtime but none fast enough yet for a class d amp application... unless you want to switch at 20 or 30k for some silly reason.
There is absolutely application specific transistors, caps, resistors.... as far as electrons, ever heard of holes?? That's beyond the scope of the debate though.
You'd do very well to figure out what device suits a particular application if you want to play with high speed power electronics, before you go doing silly things like a 1kw bjt half bridge at 22.69kHz.
You wouldn't use a 10W power resistor as turn on delay for a power switching mosfet would you?
In electronics everything is application specific to a certain degree.
classd4sure said:
yes, I did.
classd4sure said:
No. I didn't swap IC drivers for better sound.
classd4sure said:
it doesn't have to be after it. It can be in front of it, besides it and underneath it.
classd4sure said:
I guess it depends on what you mean by "application specific" which you haven't been able to define for us so I would refrain from having a discussion on something that appears to be fuzzy at present time.
classd4sure said:
and by the same token, everything is NOT application specific to a certain degree. It shows you that it is futile to have a discussion based on fuzzy definitions.
classd4sure said:
if it is not fuzzy to you, why cannot you lay it out?
Sometimes you read too much into what you read and assume people said things they didn't. For example, I didn't swap the IC drivers for better sound. I said that I swapped them and I reported a sound difference. That's it.
another point: you mentioned dead time control AFTER the IC. Well, guess what, you can do that in FRONT of the IC, on the input pins too.
The point is that there are many ways to slice and dice a thing. Not all of them are perfect for all applications. we just need to have an open mind to accept all the alternatives.
I understand your admiration for UcD, and there is nothing wrong about it.
However, it doesn't not mean everything from Phillips is wrong. And the particular point about that resistor controlling deadtime is dead on.
Give credit where credit is due. and be fair to all parties, be it Phillips or UcD.
Oh I'm able to lay it out for you, although I'm certain the cloud your head is in will float you clean over it. I'm completely disinterested in this, so here's a meager effort at best:
Granted, yet my point stands firm, as do I. You select a device based on design criteria, and implement it. It's beyond me why you'd ever resort to swapping one driver after another. Perhaps instead, figure out what's happening, test, measure, observe, research, fix. If the part can't perform as promissed, then you repeat the process. Otherwise you're just relying on blind luck, and never learning anything. Obviously you can expect a sound difference when blindly swapping either mosfets or drivers.
That tip was given to you with respect to a driver IC that didn't include separate inputs for high/low, but rather a single input, as I very clearly stated. Tell me wise one, how would you then implement deadtime control in front of the IC, when it has a single input? I guess all of a sudden you have application specific electrons do you?
Your "wisdom" was to leave dead time up to a supposed capable IC, if possible, otherwise that little resistor on the UCD would do. You presented that unilatterally. Does that make sense to you... the above quote would suggest you now disagree with yourself, and almost got my point. Though, I'd still very much like to see you implement deadtime "above, below, sideways, transwarp.."
No, you couldn't begin to
Don't two negatives make a positive... Everything I stated on the matter is dead on the money, but I'm not here to hold your hand when you haven't even tried the discrete drivers out yourself.. and dismiss everything I'm telling you simply to fuel a debate you're not up to. Good luck swapping your IC's and getting your schematics off the web.
If you want to bait me, you'll have to first know your facts, keep 'em straight, and in general, try alot harder.
Granted, yet my point stands firm, as do I. You select a device based on design criteria, and implement it. It's beyond me why you'd ever resort to swapping one driver after another. Perhaps instead, figure out what's happening, test, measure, observe, research, fix. If the part can't perform as promissed, then you repeat the process. Otherwise you're just relying on blind luck, and never learning anything. Obviously you can expect a sound difference when blindly swapping either mosfets or drivers.
That tip was given to you with respect to a driver IC that didn't include separate inputs for high/low, but rather a single input, as I very clearly stated. Tell me wise one, how would you then implement deadtime control in front of the IC, when it has a single input? I guess all of a sudden you have application specific electrons do you?
Your "wisdom" was to leave dead time up to a supposed capable IC, if possible, otherwise that little resistor on the UCD would do. You presented that unilatterally. Does that make sense to you... the above quote would suggest you now disagree with yourself, and almost got my point. Though, I'd still very much like to see you implement deadtime "above, below, sideways, transwarp.."
No, you couldn't begin to
Don't two negatives make a positive... Everything I stated on the matter is dead on the money, but I'm not here to hold your hand when you haven't even tried the discrete drivers out yourself.. and dismiss everything I'm telling you simply to fuel a debate you're not up to. Good luck swapping your IC's and getting your schematics off the web.
If you want to bait me, you'll have to first know your facts, keep 'em straight, and in general, try alot harder.
classd4sure said:
you still couldn't define "application specific" for us. Try harder next time.
classd4sure said:
for a very simple reason: I wanted to see how each driver IC performs vs. others.
Not sure why that would have escaped the wise one,
.classd4sure said:
I never expected you to hold my hand. and I thank you for all help you have offered me so far.
BTW, you are again dead wrong when you concluded that I haven't even tried the discrete drivers.
But that's just one of those ***-U-ME mistakes you so fond of.
classd4sure said:
you really as important as you think you are.
classd4sure said:
Oh right, you mean to get the high side switching in the first place....
not really. But no matter how many clown faces you put on, you still cannot dispute the fact that that little resistor does what Phillips said it does, contrary to what you said.
and you still couldn't define "application specific" for us.
IVX said:Anybody can remind me the reason of this dispute? BTW, Philips appnote, and hypex UcD400 have the same dead time adjustment method (Philips_R9=DT_Pot_UcD400).
how could it be that the UcD is following the lowly Philips on DT adjustment? didn't the wise say that that is only the DT in the "weakest possible sense"?
apparently, the UcD folks also like the "weakest possible" DT adjustments. I wonder if they will ever offer something better than the 'weakest possible" DT adjustment in the next revision.
darkfenriz said:
Hi Adam,
yes and no ...in all regards...
Of course I am not a rookie in power electronics and general analogue electronics, but I am a class D rookie. New playground and I like it.
Yes there is always a trade of between cross conduction and dead time and yes higher slew rate is requiring tougher drivers.
But not only drivers have their limits, also the free wheeling diodes allow usually not more than 5V/ns, when we force them through reverse recovery. So there are limits, which we should not exceed, even if our driver could deliver enough gate drive.
Next point: The moment of switching ON (or OFF) is not a moment.
At least in my design the length of the miller plateau is by far longer than the dead time. Means if we consider the transition of the switch from isolating to really low RdsON, my design needs more than 100ns. I am driving the IRFB52ND with 12 Ohms for turn ON and parallel 6.8 Ohms through a diode for turn OFF. The output characteristics of the driver IC are not neglectible so I have to add that my driver is the IRS 20954 with VCC approx. 12.7V.
My slew rates are round about 2V/ns...3V/ns, means sloping time is about 50ns at no load condition. I just feel better with some margin vs. data sheet limit.
The fact that the transition is not black/white ON/OFF is in reality relaxing cross conduction issues, but of course opens the discussion what is dead time.
First: Let's separate driver dead time ( = Time between falling edge of first output and rising edge of second output) from resulting half bridge dead time. For my wording I define the resulting half bridge dead time as that time during which both switch are isolating. Means the time while both Ugs are below the levels of the relevant Miller plateaus.
The limited speed of the transition between ON and OFF allows some ns overlap/crossconduction without to much trouble, as long as you can make sure that increasing temperatures do not mess up the adjustment. In my half bridge I can easily go for some cross conduction peaks of 7A/60ns at 30C and they do just increase to 8...9A/60ns at 100C and the system does not overheat and can run stable, even with small heat sinks. This would be the behavior if I settle the IC dead time to 15ns and do not use the fast turn OFF, but 12 Ohms gate drive only.
If we would have black/white ON/OFF any overlapp would immediately lead to cross conduction peaks of several hundrets of amps. In this regard I like the real world behaviour.
I settled to just no crossconduction. But if I feel that the dead time distorsion is not satisfiying me, then there is still some potential to improve by the expense of some heat.
poobah said:During the dead-time, the inductor derives its voltage from the diode/switch on the rail opposite the one that was just turned on (active). The distortion comes from the fact that the other rail voltage has a diode drop added to it. This deviates from the expectation that the rails will be symmetric. This distortion falls with rising rail voltage as the diode drop looks smaller in comparison. All this ignores the on-state voltage drop of the switches.
Fet based designs, where the freewheeling is accomplished by a synchronous FET rather than an antiparallel or body diode minimize all this by virtue of the low conduction drop.
Remember, a MOSFET in the on state is happy to conduct in EITHER direction... this is the beauty thing about FET Class D and synch. rectification in general.
If you are talking about UPS duty here... most are thrilled silly with 5% THD. 10% is really the borderline if you want to say "TRUE SINE".
Are you sure that it is a big difference if the choke is connected to 55V or to 55.3V during freewheling time???
I would tend to ignore this, but it is just a feeling from my stomach.
But you can find out if this if you chose a simulation with +/-10kV rails. Then the diode drops are neglectible. If you still find similar dead time distorsion as with +/-50V, then the diodes do not have a mayor influence.
I would rather say that we cannot always easily predict the output voltage of the half bridge during dead time.
Please note the inductor does not only carry the inductive HF ripple, it also carries most of the speaker current.
Imagine a 20Hz signal in a resistive load. May be a 30V sine wave. Let's zoom to an area which is strongly negative, say -20V vs GND.
And assume 4 Ohms resistive load. We have -5A in the resistor.
At 20Hz the cap of the output filter has a very high impedance, but the choke a very impedance. We can simplify that all the load current is also seen in the choke. In addition we have the superimposed HF current in the choke. In example +/-2A. So in this zoomed area the inductor current is rippling between -7A and -3A.
I remains always negative, means always current running into the amp. So turning after turning OFF the upper switch, the halfbridge will NOT slope downwards, the current will run through the upper freewheeling diode until the lower switch turns ON (BTW. This is the situation, where we have to take care of the reverse recovery spec of the freewheeling diode....).
...if we zoom to another area of the LF sine wave, say to something like -1.99A
then the inductor current will ramp something between +0.01A and -3.99A. At the moment of turning OFF the upper switch, we will have the +0.01A, which will now force the half bridge output voltage sloping towards lower values during dead time. Well with 0.01A this will be only partially succesfull. Inductive energy is low. Sloping speed will be very slow and depend on parasitic capacitances. In result the output voltage of the half bridge is just tumbling somewhere between both rails until the lower switch will be turned ON. This is the hard-to-predict-area, which can easily cause distorsion in my imagination. At least if this undefined time is not so short. I can also imagine that this effect is getting uncritical again if we make the dead VERY long dead times as some tri state designs have. Because then the HF sloping energy can always fully ring out without being hit from the next switch.
Aspiceman: I bet you have a nice SIM on hand with unlucky dead time adjustment and zoom to some dead time events when the choke current is close to zero... and half bridge sloping is looking slightly strange...
BTW: Of course dead time distorsions are independent from frequency if we settle the dead time as a certain percentage from the switching frequency. But in reality we are facing more the situation that the smallest dead time which we might dare to use is a fixed value... may be 50ns... and if we tie the absolute value to 50ns then the dead time percentage is becoming a function of frequency and in result also the dead time distorsions are becoming a function of frequency.
fokker said:
There's just one clown I'm putting on.
Please demonstrate exactly where I said said it didn't affect deadtime? I merely suggested it's best used to fine tune deadtime, not necessarily the first place you should count on.
Then fix it so you can evaluate its performance appropriatly.
I simply hadn't made the assumption you got them working.
Um.... power electronics. Defined sufficiently to make the point you can't just be throwing parts around willy nilly. The rest is up to you.
Hi Markus
Thank you for your reply, I always admired you for ability to talk about difficult issues in relatively simple words, very educational, unlike some knowledgable wiseguy posers.
I think you already have good slew values. If slew time were lower, than the actual dead time should be higher to avoid cross conduction, right?
What do you think such a discrete half bridge mosfet driver works like?
It seems to me, that it could give both high slew, resonable dead time and low conduction losses. I am just beggining to learn though.
best regards
Thank you for your reply, I always admired you for ability to talk about difficult issues in relatively simple words, very educational, unlike some knowledgable wiseguy posers.
I think you already have good slew values. If slew time were lower, than the actual dead time should be higher to avoid cross conduction, right?
What do you think such a discrete half bridge mosfet driver works like?
It seems to me, that it could give both high slew, resonable dead time and low conduction losses. I am just beggining to learn though.
best regards
Attachments
That's Ok but I find there's redundancy in it, unless those series resistors to the gate is a pot for helping to calibrate deadtime.
Better done by moving that elsewhere, say by varying the level of collector current of the first transistor, and /or between the bases of the following two. Your turn off schottky diode is going to hold the gate source voltage up an extra diode drop in that location.
In fact you could replace the 10ohm resistor and paralleled schottky with emitter followers, and whatever snubbers required to control ringing ..slew rates.. emi
Better done by moving that elsewhere, say by varying the level of collector current of the first transistor, and /or between the bases of the following two. Your turn off schottky diode is going to hold the gate source voltage up an extra diode drop in that location.
In fact you could replace the 10ohm resistor and paralleled schottky with emitter followers, and whatever snubbers required to control ringing ..slew rates.. emi
Choco,
Briefly here... but we are both wrong and right... Where the drive-end of the inductor "flies" or "freewheels" during dead-time depends on whether the current in the inductor is flowing "in" or "out"... AH-HA! I was looking at the BUCK cycle while you were looking at the BOOST.
Now... 50V or 50.3V. Well, what "charges" an inducter is volt-seconds. If you were off by a few nanoseconds... everyone here would thrash you soundly until inches from death. So, the same must apply to the voltage.
Back to work...
Briefly here... but we are both wrong and right... Where the drive-end of the inductor "flies" or "freewheels" during dead-time depends on whether the current in the inductor is flowing "in" or "out"... AH-HA! I was looking at the BUCK cycle while you were looking at the BOOST.
Now... 50V or 50.3V. Well, what "charges" an inducter is volt-seconds. If you were off by a few nanoseconds... everyone here would thrash you soundly until inches from death. So, the same must apply to the voltage.
Back to work...
Not really. If this was the reason, then it would be much less sensitive to dead time. 0,6...1V for a 1...5% of cycle is nothing, especially since this would be constant if you were right. Constant deviation from ideal for a constant time cannot cose nonlinearity.
The problem is much worse, and egsists even with ideal switches and ideal diodes. There is five domain: "ZERO": if inductor current is between -peak and +peak of ripple, then output current in the moment of switching off is on the normal direction for the actual MOSFET, so voltage is immediately changes to the other rail. If we calculate average value of output voltage for a cycle, we find that it doesn't differ from ideal, because there is a positive and a negative deviance as well. But there is a different domain: "POS" If inductor current is higher then ripple peak, then voltage is constantly sit on negative rail during both dead times (there is 2 in one cycle). Average voltage differs -Vcc*2*dead time/Period from ideal. At output current of less then -peak of ripple ("NEG") the situation is the opposit of "POS", voltage is more then ideal for same amount. You can see this on IVX's picture.
But what if output current is equal to +peak of ripple ("POS BORDER")?
To be continued...
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