not eliminated, simply attenuated.CBS240 said:Of course if one used a voltage regulator, then the question is eliminatd.
The PSRR is still required to attenuate the noise and other artefacts that pass the regulators. Hopefully all the effects end up below the audibility threshold over the full audio frequency band.
Bootstrapper,
AndrewT's suggestions are correct, as are his comments.
1. You've done the correct thing by eliminating the current mirrors on the LTP's
2. Go back to using the Zeners on the cascode bases the way you had them on your original circuit. As stated earlier in this thread, the idea of the cascode is to fix Vce for the amplifier transistor connected to the cascodes emitter. With you latest incarnation, this is not the case, and the cascode current bounces around in symapthy with any ripple on the rails.
3. You can probably omit th e decouplnig caps across the diode string for the CCS and the cascode zener reference - the source impedance of these is very low so you really need a very large value cap to be effective.
4. Make sure your LTP Vce can take the voltage - you may need cascodes here as well or alternatively devices with much higher Vce.
5. Run your front end at between 5mA and 10mA
Good luck
AndrewT's suggestions are correct, as are his comments.
1. You've done the correct thing by eliminating the current mirrors on the LTP's
2. Go back to using the Zeners on the cascode bases the way you had them on your original circuit. As stated earlier in this thread, the idea of the cascode is to fix Vce for the amplifier transistor connected to the cascodes emitter. With you latest incarnation, this is not the case, and the cascode current bounces around in symapthy with any ripple on the rails.
3. You can probably omit th e decouplnig caps across the diode string for the CCS and the cascode zener reference - the source impedance of these is very low so you really need a very large value cap to be effective.
4. Make sure your LTP Vce can take the voltage - you may need cascodes here as well or alternatively devices with much higher Vce.
5. Run your front end at between 5mA and 10mA
Good luck
Thanks to both of you!
If this circuit works as the simulator says, the maximum Vce voltage across LTP transistors will be 51 V. Datasheet tells that BC546 can take up to 65 V. But I can replace all BCx transistors with 2N5401/2N5551.
I will add some bias currents and voltages on the next update.
By the way, should I still have caps from the Q21/Q17 bases to ground?
If this circuit works as the simulator says, the maximum Vce voltage across LTP transistors will be 51 V. Datasheet tells that BC546 can take up to 65 V. But I can replace all BCx transistors with 2N5401/2N5551.
I will add some bias currents and voltages on the next update.
By the way, should I still have caps from the Q21/Q17 bases to ground?
Hi,
I would opt for a higher voltage (300mV) across the LTP emitter resistors. Similarly Q10 & 17 could do with a bit more bias (5mA). That would increase Vre15 to 500mV, maybe a bit high. See how the sim responds to reducing R15 & R17.
At these new currents & Vdrops you'll need to change R7 to R10.
You must trim the tail currents and the source resistances to make the four emitter currents the same for all 4 Qs in the LTPs. R12 should match R2.
RC of C4 & R1+2=63mS. RC of C6 & R13=220mS. a bit unbalanced.
Output bias seems very high. Vre is 55mV. Much larger than the 15 to 25mV that is optimum bias voltage.
R33 is quite large.
Q3 & 4 are running a bit hot at 150mW.
R34 & 35 can be combined @ 36k, similarly R18 + 19 can be 43k.
I would also add a series resistor (430r) to VR31 to prevent severe over bias and make the adjustment a little easier.
I would put back the caps across D1,2 & D3,4 & D7 & D8.
C2 looks a bit big (0.75uS) and C1 very small @ 0.08uS
I don't like your protection. Too simple and no possibility to pass (ignore) transient current which can far exceed continuous current and do no damage. Will Q21 survive, if Q6 triggers?
I would opt for a higher voltage (300mV) across the LTP emitter resistors. Similarly Q10 & 17 could do with a bit more bias (5mA). That would increase Vre15 to 500mV, maybe a bit high. See how the sim responds to reducing R15 & R17.
At these new currents & Vdrops you'll need to change R7 to R10.
You must trim the tail currents and the source resistances to make the four emitter currents the same for all 4 Qs in the LTPs. R12 should match R2.
RC of C4 & R1+2=63mS. RC of C6 & R13=220mS. a bit unbalanced.
Output bias seems very high. Vre is 55mV. Much larger than the 15 to 25mV that is optimum bias voltage.
R33 is quite large.
Q3 & 4 are running a bit hot at 150mW.
R34 & 35 can be combined @ 36k, similarly R18 + 19 can be 43k.
I would also add a series resistor (430r) to VR31 to prevent severe over bias and make the adjustment a little easier.
I would put back the caps across D1,2 & D3,4 & D7 & D8.
C2 looks a bit big (0.75uS) and C1 very small @ 0.08uS
I don't like your protection. Too simple and no possibility to pass (ignore) transient current which can far exceed continuous current and do no damage. Will Q21 survive, if Q6 triggers?
Following notices Andrew:
-It is hard to get offset low while R2=R12 (I will still try it, but if I set R12 constant and vary the value of R2, I can easily find appropriate value considering the offset)
-I don't understand that time constant of yours (C4+R1+R2). As far as I know, C4/R1 form one filter and C1/R2 another. Should I set equal time constants for those components that are between LTP bases to ground? It is Really difficult to get absolutely same impedances from those bases to ground.
-Why is 150 mW too much for Q3/Q4? Maximum power loss (by sim) would be about 300 mW with full output power. Those transistors take 600 mW (TO-92)
-Should I improve the protection by adding caps in parallel with R21/R22 to pass transient currents? I'd rather avoid adding caps from Q6/Q21 bases to ground. I could also add small series resistors between Q21/Q17 collectors and protection diodes to limit current.
-How would a series resistor with R31 make things different? If we assume that the pot does not fail.
And finally, I'm a bit (well, quite a lot!) confused by this adding and removing parallel diode caps. Should I believe you or Bonsai or somebody else?
-It is hard to get offset low while R2=R12 (I will still try it, but if I set R12 constant and vary the value of R2, I can easily find appropriate value considering the offset)
-I don't understand that time constant of yours (C4+R1+R2). As far as I know, C4/R1 form one filter and C1/R2 another. Should I set equal time constants for those components that are between LTP bases to ground? It is Really difficult to get absolutely same impedances from those bases to ground.
-Why is 150 mW too much for Q3/Q4? Maximum power loss (by sim) would be about 300 mW with full output power. Those transistors take 600 mW (TO-92)
-Should I improve the protection by adding caps in parallel with R21/R22 to pass transient currents? I'd rather avoid adding caps from Q6/Q21 bases to ground. I could also add small series resistors between Q21/Q17 collectors and protection diodes to limit current.
-How would a series resistor with R31 make things different? If we assume that the pot does not fail.
And finally, I'm a bit (well, quite a lot!) confused by this adding and removing parallel diode caps. Should I believe you or Bonsai or somebody else?
I would add like 6ohm resistor or somethinng like that on the emitters of q17/q21.. Won't show in the simulator but irl I have found it seems to improve stability reducing it like that.. hmm I like that topology, I could find myself building an amplifier like this one but with mosfets ofcourse ;-P (already did and I like it)
Hi,
at the two inputs to your amp the following are equivalent on the inverting and non-inverting sides.
R2=R12
C1=C2
R1+C4=R13+C6.
For the DC condition, only R2=R12 is relevant. This is important.
If you have output offset when these are equal, then the sim is telling you that something else is unbalanced. I suspect the currents in the two halves of the two LTPs are the main culprits. These must be trimmed by adjusting the CCS currents (add a trimmer pot //R11 and also R14) or trim the emitter resistors R15 & R17. Yes, changing the VAS alters the current balance in the LTP. D.Self showed that as little as 2% unbalance (+-1%) in the LTP made measureable increase in distortion in the built amplifier. You have 2.2% & 2.4%. You can trim these to less than 0.1% in the sim. Aim for <1% in the built amplifier. To achieve this the emitter and collector resistors must be matched to <<1%. Low gain devices (2n5xxx) for the LTP may make this LTP perform less well due to the increased input offset current required to feed the bases.
The input impedance seen by the DC blocking input cap is ~=R1+R2. The high pass F-3db~=k/{C4*[R1+R2]}
The low pass F-3db~=k/{C1*[R1+Rs]} where Rs is the source impedance at that F-3db frequency. Note that both these are approximations since there is interacton between the components of the two passive filters. They do not operate completely independantly. Your sim will be able to calculate this exactly if you ask it nicely.
R31 can be set to zero ohms. Then the Vbe multiplication factor is near infinity and the output stage tries to pass infinite current, but burns up long before that theoretical limit is ever reached. You can use the extra series resistor to limit the maximum output current if the pot is accidentally mis-set. For a two stage EF output you need about 5*Vbe to set the output bias. If you allow about 6 to 7times then that gives a tolerance for a stack up of unfavourable voltages. Using 7times requires the extra resistor to be 3300/6=550r, use 560r and the max ratio is [3300/560]+1=6.9
You may find that r31=500r now gives an acceptable range of adjustment.
at the two inputs to your amp the following are equivalent on the inverting and non-inverting sides.
R2=R12
C1=C2
R1+C4=R13+C6.
For the DC condition, only R2=R12 is relevant. This is important.
If you have output offset when these are equal, then the sim is telling you that something else is unbalanced. I suspect the currents in the two halves of the two LTPs are the main culprits. These must be trimmed by adjusting the CCS currents (add a trimmer pot //R11 and also R14) or trim the emitter resistors R15 & R17. Yes, changing the VAS alters the current balance in the LTP. D.Self showed that as little as 2% unbalance (+-1%) in the LTP made measureable increase in distortion in the built amplifier. You have 2.2% & 2.4%. You can trim these to less than 0.1% in the sim. Aim for <1% in the built amplifier. To achieve this the emitter and collector resistors must be matched to <<1%. Low gain devices (2n5xxx) for the LTP may make this LTP perform less well due to the increased input offset current required to feed the bases.
The input impedance seen by the DC blocking input cap is ~=R1+R2. The high pass F-3db~=k/{C4*[R1+R2]}
The low pass F-3db~=k/{C1*[R1+Rs]} where Rs is the source impedance at that F-3db frequency. Note that both these are approximations since there is interacton between the components of the two passive filters. They do not operate completely independantly. Your sim will be able to calculate this exactly if you ask it nicely.
R31 can be set to zero ohms. Then the Vbe multiplication factor is near infinity and the output stage tries to pass infinite current, but burns up long before that theoretical limit is ever reached. You can use the extra series resistor to limit the maximum output current if the pot is accidentally mis-set. For a two stage EF output you need about 5*Vbe to set the output bias. If you allow about 6 to 7times then that gives a tolerance for a stack up of unfavourable voltages. Using 7times requires the extra resistor to be 3300/6=550r, use 560r and the max ratio is [3300/560]+1=6.9
You may find that r31=500r now gives an acceptable range of adjustment.
"-Why is 150 mW too much for Q3/Q4? Maximum power loss (by sim) would be about 300 mW with full output power. Those transistors take 600 mW (TO-92)"
Yes they do, at 25degC. As they heat up due to power dissipation, they must be derated. Unless well heatsinked, they cannot achieve anything like 600mW. After all, you don't expect your output devices to run at 200W without a heatsink, do you.
Snag with sims is, they don't show you the smoke.
Brian.
Yes they do, at 25degC. As they heat up due to power dissipation, they must be derated. Unless well heatsinked, they cannot achieve anything like 600mW. After all, you don't expect your output devices to run at 200W without a heatsink, do you.
Snag with sims is, they don't show you the smoke.
Brian.
Sure I know that. Let's take 2N5401 as an example: Absolute maximum dissipation is 625 mW at 25 degrees. According to given derate value (5 mW/degree), it could still take 300 mW at 95 degrees. Those may be only rough approximations, but I believe those transistors could take it during normal use.
But I'm sure you've got more first hand experience on this subject, since I've never measured such temperature-power dissipation - values. Therefore I do not know if that mentioned transistor will get as high as 100 degrees with 300 mW dissipation. Maybe you know it better.
By the way, I've never seen heatsinks for TO-92 - at least my distributor does not sell them. But I guess it would not be an issue to attach a small piece of aluminium to the case.
Andrew, I altered the circuit as you suggested. By adding 200-ohm trimpots || R11 & R14, and setting R11=R14=100, I could match those LTP currents easily. After all modifications, I have now some microvolts offset, and THD 0.01 % at 100 W output. I've got few 2.2 uF WIMA caps, so I placed one at the input and fixed the rest of the values to fit that cap value. That led me having C6=4.7 uF. That seems quite low to me - more adjustment then
I still return to those diode parallel caps, should I have them or not?
Thanks, these posts have been very educating!
But I'm sure you've got more first hand experience on this subject, since I've never measured such temperature-power dissipation - values. Therefore I do not know if that mentioned transistor will get as high as 100 degrees with 300 mW dissipation. Maybe you know it better.
By the way, I've never seen heatsinks for TO-92 - at least my distributor does not sell them. But I guess it would not be an issue to attach a small piece of aluminium to the case.
Andrew, I altered the circuit as you suggested. By adding 200-ohm trimpots || R11 & R14, and setting R11=R14=100, I could match those LTP currents easily. After all modifications, I have now some microvolts offset, and THD 0.01 % at 100 W output. I've got few 2.2 uF WIMA caps, so I placed one at the input and fixed the rest of the values to fit that cap value. That led me having C6=4.7 uF. That seems quite low to me - more adjustment then
I still return to those diode parallel caps, should I have them or not?
Thanks, these posts have been very educating!
This is a very advanced (complicated) circuit for your first ever design. You can probably tell that from all the different opinions you've received. It has double LTPs, complex VAS amps and a triple darlington output stage. And it has a lot of current source and voltage reference circuits and high feedback.
Phew.
Hi,
he jumped in at the deep end and managed to doggy paddle.
Good on him.
150mW will raise the junction temperature by 30Cdegrees. (0.15W/0.005W/C=30C)
If the internal ambient temperature is 35degC then quiescent Tj is 65degC. Now apply your maximum power of 300mW and that instantaneously raises the junction temp by a further 30Cdegrees to 95degC. Do you really want your junction temps jumping around like that. What do you think happens to some of the parameters at these elevated temperatures? What happens to output offset, gain, speed (fT), etc? Will these changes have any effect on distortion or some other characteristic?
I wouldn't go quite that high in a To92, but if you convince yourself that nothing untoward happens, then go with your decision. I would use a medium power Q here, maybe 5W to 7W, and if it runs cold @ quiescent leave it without a sink. If it runs noticeably warm then add a small sink (20 to 30C/W). Or I would reduce the quiescent to below 100mW.
C6=4.7uF does not seem right.
What RC values have you got at input filters and NFB?
he jumped in at the deep end and managed to doggy paddle.
Good on him.
150mW will raise the junction temperature by 30Cdegrees. (0.15W/0.005W/C=30C)
If the internal ambient temperature is 35degC then quiescent Tj is 65degC. Now apply your maximum power of 300mW and that instantaneously raises the junction temp by a further 30Cdegrees to 95degC. Do you really want your junction temps jumping around like that. What do you think happens to some of the parameters at these elevated temperatures? What happens to output offset, gain, speed (fT), etc? Will these changes have any effect on distortion or some other characteristic?
I wouldn't go quite that high in a To92, but if you convince yourself that nothing untoward happens, then go with your decision. I would use a medium power Q here, maybe 5W to 7W, and if it runs cold @ quiescent leave it without a sink. If it runs noticeably warm then add a small sink (20 to 30C/W). Or I would reduce the quiescent to below 100mW.
C6=4.7uF does not seem right.
What RC values have you got at input filters and NFB?
Hi Andrew,
Increasing temperature will no doubt change all those parameters, as more charge carries are created through thermal generation. That leads to lower Vbe and so on. Fine, you've convinced me not to use BCs or 2N5s. Somehow I feel that BD139/140 would be too clumsy in LTP, what do you think? I quickly checked those BDs, MJE340 & 2SB649 and they have significantly lower hfe than BC546B for example. So I guess I cannot use those.
Maybe I should find a way to reduce the power dissipation by modifying this circuit instead of replacing transistors. I could reduce LTP currents a bit, or perhaps reduce the voltage across those transistors. And then there's the option to use cascode as somebody suggested.
I ended up having these values:
R1=2k2, R2=R12=12k, R13=1k, C1=C2=68p, C4=2u2, C6=4u7
If I remember right, I read some post saying that appropriate value for C6 is something like 100u - 200u. I will try new values for those when I have time.
Increasing temperature will no doubt change all those parameters, as more charge carries are created through thermal generation. That leads to lower Vbe and so on. Fine, you've convinced me not to use BCs or 2N5s. Somehow I feel that BD139/140 would be too clumsy in LTP, what do you think? I quickly checked those BDs, MJE340 & 2SB649 and they have significantly lower hfe than BC546B for example. So I guess I cannot use those.
Maybe I should find a way to reduce the power dissipation by modifying this circuit instead of replacing transistors. I could reduce LTP currents a bit, or perhaps reduce the voltage across those transistors. And then there's the option to use cascode as somebody suggested.
I ended up having these values:
R1=2k2, R2=R12=12k, R13=1k, C1=C2=68p, C4=2u2, C6=4u7
If I remember right, I read some post saying that appropriate value for C6 is something like 100u - 200u. I will try new values for those when I have time.
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