Considering ver7.pdf, I forgot to change the values of the input filter & feedback circuit. Those values are now like Donk said.
I've been drawing layout for this using SMD resistors & caps (if possible). With double-sided PCB I can easily get quite nice ground plane, which definetely helps in beating noise. And as the supply traces are on the top side, there will be extra capacitance between voltage traces and the ground plane (which are on the opposite sides). As far as I know, the best option might be 4-layered PCB arranged so that I would have two ground planes, signal layer in between them and finally one layer for the supply voltages. That may lead to blind vias and such things, and many manufacturers are not able to make them. But that's another story.
I may add layout files here when I'm finished (even if nobody would be interested)
I've been drawing layout for this using SMD resistors & caps (if possible). With double-sided PCB I can easily get quite nice ground plane, which definetely helps in beating noise. And as the supply traces are on the top side, there will be extra capacitance between voltage traces and the ground plane (which are on the opposite sides). As far as I know, the best option might be 4-layered PCB arranged so that I would have two ground planes, signal layer in between them and finally one layer for the supply voltages. That may lead to blind vias and such things, and many manufacturers are not able to make them. But that's another story.
I may add layout files here when I'm finished (even if nobody would be interested)
To check th e amp slew rate, remove your input filter - set the 470pf cap to 1 pf and then re-run your sim. Note, this is for simulation purposes only - you should not run the amp practically without this input cap since it is part of the compensation (there was quite some discusion about this on some other threads).
I see you are running either side of th e LTP's at c. 3mA. If you want your amp to slew faster, you could run the LTP's richer - 5mA per side is ok. This will increase your VAS standing current (in your specific circuit it will go from about 9mA to about 14mA or so). This is ok but that can be reduced again if you want by increasing the emitter degeneration resistor on each VAS transistor.
You have two caps going from the VAS to ground either side of the Vbe multiplier - I'd get rid of them. This is not an optimal way to compensate an amp.
Your emitter LTP degeneration resistors look a bit low in value to me. I have a similar topology amp and I run mine with 150 Ohms (and 5mA per LTP side). When you build this amp, if it oscillates, I'd increase the value of these to reduce your overall loop gain and get the amp stable again. BTW, the increased LTP degeneration resistors will make the diff amp more linear.
Your circuit is starting to look good - you've made a lot of prgress over the last few weeks - good luck.
I see you are running either side of th e LTP's at c. 3mA. If you want your amp to slew faster, you could run the LTP's richer - 5mA per side is ok. This will increase your VAS standing current (in your specific circuit it will go from about 9mA to about 14mA or so). This is ok but that can be reduced again if you want by increasing the emitter degeneration resistor on each VAS transistor.
You have two caps going from the VAS to ground either side of the Vbe multiplier - I'd get rid of them. This is not an optimal way to compensate an amp.
Your emitter LTP degeneration resistors look a bit low in value to me. I have a similar topology amp and I run mine with 150 Ohms (and 5mA per LTP side). When you build this amp, if it oscillates, I'd increase the value of these to reduce your overall loop gain and get the amp stable again. BTW, the increased LTP degeneration resistors will make the diff amp more linear.
Your circuit is starting to look good - you've made a lot of prgress over the last few weeks - good luck.
Hi Bonsai,
I heard one opinion once which stated that the whole input filter system should be bypassed during square wave and thd sims. Personally I have bypassed only the dc-blocking 2u2 cap, but I will try altering the other one too if it gives more accurate results.
Few posts ago I was wondering about the base resistor values, but I did some simulating and found out that they are quite correct now. If I change the values of (refer to ver7) R39,R30,R40 & R29, there will be some strange behaviour in FFT spectrum.
Thanks for your advice, I'll update ver8 including result figures when I have time.
I heard one opinion once which stated that the whole input filter system should be bypassed during square wave and thd sims. Personally I have bypassed only the dc-blocking 2u2 cap, but I will try altering the other one too if it gives more accurate results.
Few posts ago I was wondering about the base resistor values, but I did some simulating and found out that they are quite correct now. If I change the values of (refer to ver7) R39,R30,R40 & R29, there will be some strange behaviour in FFT spectrum.
Thanks for your advice, I'll update ver8 including result figures when I have time.
I agree with Bonsai on these two points.Bonsai said:
I would also look at increasing R13 from the 330r value maybe between 470r and 620r, unless you really need +33db of gain.
Your base stopper values of 100r, 18r & 3r3 seem well scaled for the currents likely to pass.
Are you saying that the sim shows significant changes if any of these are changed up or down?
What changes, distortion? and how much does the value need top be moved to see the effect?
Hi Andrew,
During my earlier sims I found out that the floor of the FFT spectrum looked more like rectified sine rather than somewhat straight line, when I gave base resistors values about one decade smaller or larger than they have now. But now I cannot see the effect, at least it is much weaker - this may be again one of the mysteries that pspice seems to have. So minor changes in the values should not show any great difference in thd value (although I previously thought so).
Should I replace the caps C5 & C7 with one larger (say 22p or 33p) or remove them both without any replacement? I do not fully understand their function. Donk suggested using 100n (C9) across the vbe multiplier, is that ok? Refer to ver7.
Thanks.
During my earlier sims I found out that the floor of the FFT spectrum looked more like rectified sine rather than somewhat straight line, when I gave base resistors values about one decade smaller or larger than they have now. But now I cannot see the effect, at least it is much weaker - this may be again one of the mysteries that pspice seems to have. So minor changes in the values should not show any great difference in thd value (although I previously thought so).
Should I replace the caps C5 & C7 with one larger (say 22p or 33p) or remove them both without any replacement? I do not fully understand their function. Donk suggested using 100n (C9) across the vbe multiplier, is that ok? Refer to ver7.
Thanks.
C5 and C7 are loads for the VAS. They become very low at high frequency and pull the VAS stage output to ground at the very highest frequencies. This is a type of compensation that rolls off the treble but it achieves it with a very demanding load that increases distortion and massively increases stage current. Not nice.
I see that Symasym uses it and many say his amp sounds good. It appears that it can be made to sound nice, but I suspect it can also sound bad if not implemented well. Take care.
I see that Symasym uses it and many say his amp sounds good. It appears that it can be made to sound nice, but I suspect it can also sound bad if not implemented well. Take care.
At last I had time to consider this seemingly everlasting project, and I did in fact some modifications (improvements, hopefully).
1) Separating differential pair/input ground from "power" ground via small resistor
2) Implementing two-pole compensation at VAS according to desings by R.Slone. The values shown are not the final ones, I'm still trying to find the best combination.
Comments are more than welcome
1) Separating differential pair/input ground from "power" ground via small resistor
2) Implementing two-pole compensation at VAS according to desings by R.Slone. The values shown are not the final ones, I'm still trying to find the best combination.
Comments are more than welcome
Some update:
-Updated schematics (not all the component values are final)
-Proposal for component placing (routing partially done)
-Pictures of the power supply board
-Power supply board copper artwork
The corrected schematics now includes some extra components since I intend to experiment with different approaches. For instance, there are optional ways to implement compensation. Also the number of output devices is increased.
As for the component placing I had in mind to place the most sensitive components/subcircuits far away from the output stage. Referring to the attachment, starting from the heatsink there are three major lines of components: i) The output stage, ii) VAS, Vbe multiplier, protection and input current sources and finally iii) the input stage + feedback. The actual point of feedback connection will be made at the junction of Zobel and output resistors (Rz & R61).
Main circuit
Assembly
Power supply board
Power supply (1)
Power supply (2)
The supply voltages will be somewhere between 56 and 63 volts, I'm currently working on an offline 1 kW full-bridge converter intended to supply this amplifier. Should it not succeed, I will use an ordinary toroidal approach for which the mentioned capacitor board is made.
-Updated schematics (not all the component values are final)
-Proposal for component placing (routing partially done)
-Pictures of the power supply board
-Power supply board copper artwork
The corrected schematics now includes some extra components since I intend to experiment with different approaches. For instance, there are optional ways to implement compensation. Also the number of output devices is increased.
As for the component placing I had in mind to place the most sensitive components/subcircuits far away from the output stage. Referring to the attachment, starting from the heatsink there are three major lines of components: i) The output stage, ii) VAS, Vbe multiplier, protection and input current sources and finally iii) the input stage + feedback. The actual point of feedback connection will be made at the junction of Zobel and output resistors (Rz & R61).
Main circuit
Assembly
Power supply board
Power supply (1)
Power supply (2)
The supply voltages will be somewhere between 56 and 63 volts, I'm currently working on an offline 1 kW full-bridge converter intended to supply this amplifier. Should it not succeed, I will use an ordinary toroidal approach for which the mentioned capacitor board is made.
Diodes D12 and D13 may need to be doubled to obtain more voltage across the cascode.
The tail of the cascode can couple to either signal ground or to the tails of the emitter resistors. Use a link for this option.
R16 & R28 do not need to go to power ground. they can be connected to each other or replaced with a single 22k.
Similarly, R19 & R21 can couple or be replaced with a single.
D10 and D11 may not provide sufficient cascode voltage to the degenerated VAS stages.
If using LEDs for the other voltage references then why use dual series diodes for D1 to D4?
The collector loads R3, 5, 10 & 12 seem a bit low.
The LTP CCS is sinking/sourcing ~>=8mA.
Allowing ~4mA through each half of the LTP then the voltage across the collector loads is only 800mV. The degenerated VAS may need more than this. The VAS (depending on Iq) will force ~ 700mV to 1000mV across the loads. Adjust the loads to balance the currents in the four halves of the LTPs. You can measure the LTP balance at the emitters of the LTPs.
I think your VAS degeneration values are too high. Try dividing by ~ 2 to 5.
Use a film/foil or metallised film capacitor for the DC blocker/input filter. It must be <=14uF to match C9. Your 22u+22u complies with this.
You may get away with ~3u6F in combination with Rin= 24k2.
I like the Thiele Network on the output.
Add ~4r+47nF across the speaker terminals. This will give a bit more RF attenuation for RF coming in from the speaker and give a slightly lower HF load for the output stage.
C3 might be a little low (0.15us). You could augment it with 47pF across the RCA input terminals and maybe increase the 68p to around 100p to 220p.
I don't like your IV limiting implementation. It needs (a lot) more thought.
D5 could be a series pair to allow <1200mVpk across the cap. Add another series pair in inverse parallel.
I like the differentiation between Signal Ground and the other Ground.
Consider changing R17 and R24 to 150r AND adding a 500r pot in parallel to both. To complement this change R18 and R23 to ~36r. This would suit R3, 5, 10 & 12 ~>=300r.
The tail of the cascode can couple to either signal ground or to the tails of the emitter resistors. Use a link for this option.
R16 & R28 do not need to go to power ground. they can be connected to each other or replaced with a single 22k.
Similarly, R19 & R21 can couple or be replaced with a single.
D10 and D11 may not provide sufficient cascode voltage to the degenerated VAS stages.
If using LEDs for the other voltage references then why use dual series diodes for D1 to D4?
The collector loads R3, 5, 10 & 12 seem a bit low.
The LTP CCS is sinking/sourcing ~>=8mA.
Allowing ~4mA through each half of the LTP then the voltage across the collector loads is only 800mV. The degenerated VAS may need more than this. The VAS (depending on Iq) will force ~ 700mV to 1000mV across the loads. Adjust the loads to balance the currents in the four halves of the LTPs. You can measure the LTP balance at the emitters of the LTPs.
I think your VAS degeneration values are too high. Try dividing by ~ 2 to 5.
Use a film/foil or metallised film capacitor for the DC blocker/input filter. It must be <=14uF to match C9. Your 22u+22u complies with this.
You may get away with ~3u6F in combination with Rin= 24k2.
I like the Thiele Network on the output.
Add ~4r+47nF across the speaker terminals. This will give a bit more RF attenuation for RF coming in from the speaker and give a slightly lower HF load for the output stage.
C3 might be a little low (0.15us). You could augment it with 47pF across the RCA input terminals and maybe increase the 68p to around 100p to 220p.
I don't like your IV limiting implementation. It needs (a lot) more thought.
D5 could be a series pair to allow <1200mVpk across the cap. Add another series pair in inverse parallel.
I like the differentiation between Signal Ground and the other Ground.
Consider changing R17 and R24 to 150r AND adding a 500r pot in parallel to both. To complement this change R18 and R23 to ~36r. This would suit R3, 5, 10 & 12 ~>=300r.
This refers to message #13 & #15.
Correction: what I meant was connecting the 10K resistors from collectors (not emitters) to ground.
I learned this from a circuit designed by D.Self and published in Wireless Electronics back in the mid-80s.
If I can locate the magazine within a mountain of trash in my basement, I will send you a copy.
Boots,
Did you finish build this power amp?
Correction: what I meant was connecting the 10K resistors from collectors (not emitters) to ground.
I learned this from a circuit designed by D.Self and published in Wireless Electronics back in the mid-80s.
If I can locate the magazine within a mountain of trash in my basement, I will send you a copy.
Boots,
Did you finish build this power amp?
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