Hi there.
I still think of major disadvantages of the standard PS vs. battery.
1. DC saturated transformer
You need to have a DC-blocker in the mains path, otherwise you'll get
a saturated transformer, causing quite some degradation
2. The mains- sinewave is not a sine - it is a mess with quite some HF rubbish on top.
This will for sure have an impact on the transfer function.
How do you solve these issues?
Cheers
I still think of major disadvantages of the standard PS vs. battery.
1. DC saturated transformer
You need to have a DC-blocker in the mains path, otherwise you'll get
a saturated transformer, causing quite some degradation
2. The mains- sinewave is not a sine - it is a mess with quite some HF rubbish on top.
This will for sure have an impact on the transfer function.
How do you solve these issues?
Cheers
Hi dantwomey,
quote: "By ensuring the load is Never-Connected directly to the incoming mains supply, Never-Connected totally breaks the conduction path for mains Pollution, preventing contamination of the music with unwanted noise and interference."
The product you are referring to seems to imply that the load is completely disconnected from the mains. The charge-transfer power supply still has GND directly connected to the transformer (mains power supply), just look at the basic schematic.
It only interrupts a direct charge current path between both transformer and load. By doing so, the circuit can be very simple, and only requires few cheap parts.
quote: "By ensuring the load is Never-Connected directly to the incoming mains supply, Never-Connected totally breaks the conduction path for mains Pollution, preventing contamination of the music with unwanted noise and interference."
The product you are referring to seems to imply that the load is completely disconnected from the mains. The charge-transfer power supply still has GND directly connected to the transformer (mains power supply), just look at the basic schematic.
It only interrupts a direct charge current path between both transformer and load. By doing so, the circuit can be very simple, and only requires few cheap parts.
Hi -ecdesigns-
i would like to know more detail about the fourth module in your post #2276, are you using an HEF4517 to obtain "WS16 output, WS32 output, WS48 output, WS64 output, DATA16 output, DATA32 output, NDATA48 output and NDATA64 output"?
I would like to build a simplified version of the DI DAC with 4 TDA1543 just to prove it and to learn something. The HEF4517 could be a simple solution (for the 4x interpolator) and i would like to know if it's good at this or there are some counterindications.
Ciao
Andrea
i would like to know more detail about the fourth module in your post #2276, are you using an HEF4517 to obtain "WS16 output, WS32 output, WS48 output, WS64 output, DATA16 output, DATA32 output, NDATA48 output and NDATA64 output"?
I would like to build a simplified version of the DI DAC with 4 TDA1543 just to prove it and to learn something. The HEF4517 could be a simple solution (for the 4x interpolator) and i would like to know if it's good at this or there are some counterindications.
Ciao
Andrea
Charge-transfer circuit schematics
Simply by using a charge-transfer power supply!
OK, I added a schematic diagram of a possible implementation (I currently use a similar circuit for testing it in the DI4T).
> First the primary smoothing cap (Cp) is charged with the polluted rectified voltage through D1 ... D3. R1 puts a positive voltage on P-FET T1, switching it OFF, and disconnecting the load during this charge cycle.
All interference surges through the primary smoothing cap -not the connected load- The severety of the pollution really doesn't matter at this point, main purpose is to get the primary smoothing cap Cp charged.
> Next the rectified voltage drops below the voltage across the smoothing cap Cp plus voltage drop across the rectifier diodes D1 & D3 or D2 & D3, now the rectifier diode no longer conducts, and interrupts the noisy charge current. All that remains after this interference attack is a charged capacitor. The P-MOSFET is not yet switched-on as -Vgs is still too low to make it conduct.
Now we have a floating charged cap (Cp), it's basically similar to a battery connected to GND with the minus terminal. Needless to say that all the interference signals during charging are not "remembered" by capacitor Cp.
> As the sinewave voltage drops, P-channel MOSFET -Vgs gets high enough, and T1 switches-ON. T1 now connects charged cap Cp to both Cs and load, the charge of the primary smoothing cap supplies clean energy to both Cs and load.
> After the sinewave voltage rises again, -Vgs drops and T1 is switched OFF. Now the secondary smoothing cap Cs continues to supply clean electrical energy to the load.
The cycle is repeated 50/60 times a second with half-wave rectifiers, and 100/120 times a second with full-wave rectifiers.
Both D4 and D5 (Zener diode and Schottky diode) are added for protecting the gate of T1.
D3 was added to create the required switching signal for T1. T1 is switched-on by pulling the gate to GND through both R1 and R2, the protection diodes D4 and D5 will limit -Vgs. T1 is switched off by pulling the gate to plus through R1.
The peak charge transfer current through Cs is limited by the P-MOSFET RdsON, but can be further manipulated by adding an extra series resistor in the drain lead.
Negative charge-transfer power supplies are very similar, just use a N-MOSFET, and reverse polarity of diodes and caps
Simply by using a charge-transfer power supply!
OK, I added a schematic diagram of a possible implementation (I currently use a similar circuit for testing it in the DI4T).
> First the primary smoothing cap (Cp) is charged with the polluted rectified voltage through D1 ... D3. R1 puts a positive voltage on P-FET T1, switching it OFF, and disconnecting the load during this charge cycle.
All interference surges through the primary smoothing cap -not the connected load- The severety of the pollution really doesn't matter at this point, main purpose is to get the primary smoothing cap Cp charged.
> Next the rectified voltage drops below the voltage across the smoothing cap Cp plus voltage drop across the rectifier diodes D1 & D3 or D2 & D3, now the rectifier diode no longer conducts, and interrupts the noisy charge current. All that remains after this interference attack is a charged capacitor. The P-MOSFET is not yet switched-on as -Vgs is still too low to make it conduct.
Now we have a floating charged cap (Cp), it's basically similar to a battery connected to GND with the minus terminal. Needless to say that all the interference signals during charging are not "remembered" by capacitor Cp.
> As the sinewave voltage drops, P-channel MOSFET -Vgs gets high enough, and T1 switches-ON. T1 now connects charged cap Cp to both Cs and load, the charge of the primary smoothing cap supplies clean energy to both Cs and load.
> After the sinewave voltage rises again, -Vgs drops and T1 is switched OFF. Now the secondary smoothing cap Cs continues to supply clean electrical energy to the load.
The cycle is repeated 50/60 times a second with half-wave rectifiers, and 100/120 times a second with full-wave rectifiers.
Both D4 and D5 (Zener diode and Schottky diode) are added for protecting the gate of T1.
D3 was added to create the required switching signal for T1. T1 is switched-on by pulling the gate to GND through both R1 and R2, the protection diodes D4 and D5 will limit -Vgs. T1 is switched off by pulling the gate to plus through R1.
The peak charge transfer current through Cs is limited by the P-MOSFET RdsON, but can be further manipulated by adding an extra series resistor in the drain lead.
Negative charge-transfer power supplies are very similar, just use a N-MOSFET, and reverse polarity of diodes and caps
Attachments
Hi anbello,
The 4th module in post #2276 holds a 4 x interpolator with integrated scrambler (for compensating on-chip L/R channel differences).
This requires 2 x CD4517, a 74HC157, and a 74HC00. The circuit generates 4 I2S streams for driving 4 separate stereo DAC chips. Two DAC chips also receive inverted data (balanced operation), and have their L/R channels swapped (scrambler). So the L/R outputs of the DAC chips that process WS/ND48 and WS/ND64, have to be swapped: L becomes R and R becomes L.
The module also holds a counter that generates both WS (CS8416 receiver runs in slave-clock mode), and the differential DEM clock signals DEM & NDEM that are required for the latest TDA1541A differential DEM clock circuit. When using the TDA1543, the differential DEM clock outputs are not used.
Both WS and DATA outputs already have series resistors installed that are part of the required I2S attenuators.
This module is designed to drive either 4 x TDA1541A or 4 x TDA1543, so no modifications are needed.
I used TI CD4517 shift registers (2 x 64-bit) that can operate at 6 MHz typical @5V. This easily covers the 2.8224 MHz masterclock frequency I am using. It has proven to work excellent in both DI4MJ and DI4T. If higher speeds are required, you will need plenty of 74HC164 chips and a much bigger PCB.
The 4th module in post #2276 holds a 4 x interpolator with integrated scrambler (for compensating on-chip L/R channel differences).
This requires 2 x CD4517, a 74HC157, and a 74HC00. The circuit generates 4 I2S streams for driving 4 separate stereo DAC chips. Two DAC chips also receive inverted data (balanced operation), and have their L/R channels swapped (scrambler). So the L/R outputs of the DAC chips that process WS/ND48 and WS/ND64, have to be swapped: L becomes R and R becomes L.
The module also holds a counter that generates both WS (CS8416 receiver runs in slave-clock mode), and the differential DEM clock signals DEM & NDEM that are required for the latest TDA1541A differential DEM clock circuit. When using the TDA1543, the differential DEM clock outputs are not used.
Both WS and DATA outputs already have series resistors installed that are part of the required I2S attenuators.
This module is designed to drive either 4 x TDA1541A or 4 x TDA1543, so no modifications are needed.
I used TI CD4517 shift registers (2 x 64-bit) that can operate at 6 MHz typical @5V. This easily covers the 2.8224 MHz masterclock frequency I am using. It has proven to work excellent in both DI4MJ and DI4T. If higher speeds are required, you will need plenty of 74HC164 chips and a much bigger PCB.
hi john,
thanks for the explanation. i am very looking forward to seeing your complete ready dac (hopefully very soon ) .
currently i am using a cd-pro2m transport which has a i2s output. can i use directly this interface for connecting with your dac or i should build an optical output to be connected to your receiver module?
cdpro2 has a spdif output as well but i can remember you mentioned somewhere that you rather suggest an optical interface than the spdif (coax), correct?
regards
mamal
thanks for the explanation. i am very looking forward to seeing your complete ready dac (hopefully very soon
) . currently i am using a cd-pro2m transport which has a i2s output. can i use directly this interface for connecting with your dac or i should build an optical output to be connected to your receiver module?
cdpro2 has a spdif output as well but i can remember you mentioned somewhere that you rather suggest an optical interface than the spdif (coax), correct?
regards
mamal
Re: Charge-transfer circuit schematics
http://www.diyaudio.com/forums/showthread.php?postid=151191#post151191
Reminds me of the flying cap schematic posted by Jonathan Carr some years ago.-ecdesigns- said:
Simply by using a charge-transfer power supply!
OK, I added a schematic diagram of a possible implementation (I currently use a similar circuit for testing it in the DI4T).
> First the primary smoothing cap (Cp) is charged with the polluted rectified voltage through D1 ... D3. R1 puts a positive voltage on P-FET T1, switching it OFF, and disconnecting the load during this charge cycle.
All interference surges through the primary smoothing cap -not the connected load- The severety of the pollution really doesn't matter at this point, main purpose is to get the primary smoothing cap Cp charged.
> Next the rectified voltage drops below the voltage across the smoothing cap Cp plus voltage drop across the rectifier diodes D1 & D3 or D2 & D3, now the rectifier diode no longer conducts, and interrupts the noisy charge current. All that remains after this interference attack is a charged capacitor. The P-MOSFET is not yet switched-on as -Vgs is still too low to make it conduct.
Now we have a floating charged cap (Cp), it's basically similar to a battery connected to GND with the minus terminal. Needless to say that all the interference signals during charging are not "remembered" by capacitor Cp.
> As the sinewave voltage drops, P-channel MOSFET -Vgs gets high enough, and T1 switches-ON. T1 now connects charged cap Cp to both Cs and load, the charge of the primary smoothing cap supplies clean energy to both Cs and load.
> After the sinewave voltage rises again, -Vgs drops and T1 is switched OFF. Now the secondary smoothing cap Cs continues to supply clean electrical energy to the load.
The cycle is repeated 50/60 times a second with half-wave rectifiers, and 100/120 times a second with full-wave rectifiers.
Both D4 and D5 (Zener diode and Schottky diode) are added for protecting the gate of T1.
D3 was added to create the required switching signal for T1. T1 is switched-on by pulling the gate to GND through both R1 and R2, the protection diodes D4 and D5 will limit -Vgs. T1 is switched off by pulling the gate to plus through R1.
The peak charge transfer current through Cs is limited by the P-MOSFET RdsON, but can be further manipulated by adding an extra series resistor in the drain lead.
Negative charge-transfer power supplies are very similar, just use a N-MOSFET, and reverse polarity of diodes and caps
http://www.diyaudio.com/forums/showthread.php?postid=151191#post151191
Attachments
Hi -ecdesigns-
thanks for the explanation, as you said i don't need DEM clock with 1543 and, for now, i omit the scrambler for simplicity.
I don't even need the generation of WS because i build a receiver with an 8412 in slave mode and an 8402 that slave the soundcard via spdif so WS and BCK ar generated there.
In this situation a CD4517 (and an HC04 for balanced operation) is all i need to generate the delayed WS and DATA for the interpolation. Is this correct?
Another question, for balanced operation which is better:
1) 4x1543 with WS16, WS32, WS48, WS64, DATA16, DATA32, NDATA48 and NDATA64
2) 8x1543 of which 4 with WS16, WS32, WS48, WS64, DATA16, DATA32, DATA48, DATA64 and 4 with WS16, WS32, WS48, WS64, NDATA16, NDATA32, NDATA48, NDATA64
Thanks
Andrea
thanks for the explanation, as you said i don't need DEM clock with 1543 and, for now, i omit the scrambler for simplicity.
I don't even need the generation of WS because i build a receiver with an 8412 in slave mode and an 8402 that slave the soundcard via spdif so WS and BCK ar generated there.
In this situation a CD4517 (and an HC04 for balanced operation) is all i need to generate the delayed WS and DATA for the interpolation. Is this correct?
Another question, for balanced operation which is better:
1) 4x1543 with WS16, WS32, WS48, WS64, DATA16, DATA32, NDATA48 and NDATA64
2) 8x1543 of which 4 with WS16, WS32, WS48, WS64, DATA16, DATA32, DATA48, DATA64 and 4 with WS16, WS32, WS48, WS64, NDATA16, NDATA32, NDATA48, NDATA64
Thanks
Andrea
Hi there EC - I have been asking on this forum for a few months now, but nobody has replied. I love the 'Musicality' of the TDA1541A DAC but it is difficult to find anythin for sale at a normal price. I have a Cambridge Audio Dacmagic 2i and want to know if it is possible to use the 1541 DAC in place of the 1305's, but nobody seems to know. I am sure you do.
Kind Regards
Stuart.
Kind Regards
Stuart.
Hi QSerraTico Tico,
It looks similar indeed, but it requires more than twice the amount of components for the charge-transfer section. It might be slightly more efficient as it uses two secondary caps (C6 and C7) that feed the load.
I have doubts about the connection between transistor base and transformer, this could still inject (HF) interference currents through the transistor stray capacitance. Other problem is the voltage drop across the transistors (Vce). This voltage drop might well be in the range of a few volts, depending on connected load.
I use MOSFETS as these have very low RdsON (very little voltage drop across the MOSFET), and can handle very high charge currents when required (power amplifier supply). I can also use high Ohmic gate series resistors (reduces possible interference current injection through the MOSFET gate).
I am currently re-designing the charge-transfer power supply, by integrating a discrete ultra low noise voltage regulator + capacitance multiplier. If this works well, it's goodbye to the noisy integrated 3-pin voltage regulators. This would also mean that I could remove all 78XX and 79XX voltage regulators from the DA1541A modules ....
It looks similar indeed, but it requires more than twice the amount of components for the charge-transfer section. It might be slightly more efficient as it uses two secondary caps (C6 and C7) that feed the load.
I have doubts about the connection between transistor base and transformer, this could still inject (HF) interference currents through the transistor stray capacitance. Other problem is the voltage drop across the transistors (Vce). This voltage drop might well be in the range of a few volts, depending on connected load.
I use MOSFETS as these have very low RdsON (very little voltage drop across the MOSFET), and can handle very high charge currents when required (power amplifier supply). I can also use high Ohmic gate series resistors (reduces possible interference current injection through the MOSFET gate).
I am currently re-designing the charge-transfer power supply, by integrating a discrete ultra low noise voltage regulator + capacitance multiplier. If this works well, it's goodbye to the noisy integrated 3-pin voltage regulators. This would also mean that I could remove all 78XX and 79XX voltage regulators from the DA1541A modules ....
Hi stuartbooth,
Should be no problem, the TDA1305 contains a 1fs data input upsampling continuous bitstream stereo DAC. This would mean that the TDA1541A could be connected to BCK (TDA1305 pin 4), WS (TDA1305 pin 5), and DATA (TDA1305 pin 6). DGND reference (VSSD) is pin 9. The TDA1305 is specified to handle I2S, just like the TDA1541A. In this case the TDA1541A would run in NOS mode.
PS, You might ask Jean Paul, perhaps he has some TDA1541A chips left. I bought some from him recently, and they work excellent.
Should be no problem, the TDA1305 contains a 1fs data input upsampling continuous bitstream stereo DAC. This would mean that the TDA1541A could be connected to BCK (TDA1305 pin 4), WS (TDA1305 pin 5), and DATA (TDA1305 pin 6). DGND reference (VSSD) is pin 9. The TDA1305 is specified to handle I2S, just like the TDA1541A. In this case the TDA1541A would run in NOS mode.
PS, You might ask Jean Paul, perhaps he has some TDA1541A chips left. I bought some from him recently, and they work excellent.
A fellow engineer at IBM tried to patent a similar scheme in the ‘70s. A patent search turned up a patent from the ‘30s that was broad enough to cover the idea.
As I remember it, his scheme had (conceptually) a SPDT switch with the operate contact on the first capacitor. The switch would transfer between the rectifier and the second capacitor. This provided total isolation between the line and the load, which meant that he could do away with the power transformer. He built a prototype and it worked fine, but the lawyers would have nothing to do with a product that was not galvanically isolated.
He also found out that this scheme was being used by the aerospace industry, where it was a big plus to be able to eliminate the power transformer.
Dave
As I remember it, his scheme had (conceptually) a SPDT switch with the operate contact on the first capacitor. The switch would transfer between the rectifier and the second capacitor. This provided total isolation between the line and the load, which meant that he could do away with the power transformer. He built a prototype and it worked fine, but the lawyers would have nothing to do with a product that was not galvanically isolated.
He also found out that this scheme was being used by the aerospace industry, where it was a big plus to be able to eliminate the power transformer.
Dave
re: Charge-transfer circuit schematics
Hi John,
The very old Electron Kinetics Eagle 7A, designed by John Iverson used TRIAC switching at line frequency, very similar to your approach and the amplifier sounds really good. Now reading your post I realized that it has some to do with its sound. Thanks for the sharing!
Hi John,
The very old Electron Kinetics Eagle 7A, designed by John Iverson used TRIAC switching at line frequency, very similar to your approach and the amplifier sounds really good. Now reading your post I realized that it has some to do with its sound. Thanks for the sharing!
Hi maxlorenz,
Hi maxlorenz,
It's the mains frequency, so it's obvious to use this frequency for switching.
This could work when the 1Hz runs synchronous with the mains frequency (divider), and the smoothing capacitors have large enough value. Most of my charge-transfer circuits are followed by a capacitance multiplier (similar to a Teddyreg) in order to remove the remaining low-frequency ripple current.
Both my PCs and macs have stock power supplies of the switching kind. I don't plan to modify them.
Hi maxlorenz,
It's the mains frequency, so it's obvious to use this frequency for switching.
This could work when the 1Hz runs synchronous with the mains frequency (divider), and the smoothing capacitors have large enough value. Most of my charge-transfer circuits are followed by a capacitance multiplier (similar to a Teddyreg) in order to remove the remaining low-frequency ripple current.
Both my PCs and macs have stock power supplies of the switching kind. I don't plan to modify them.
Hi amplitron,
I would have to study the Electron Kinetics Eagle 7A schematics to confirm this, but if it uses a similar method of rejecting mains noise, this may very well contribute to sound quality.
So far I modified following power supplies:
DI4T, +5V digital supply, +5V, -5V and -15V supplies for the TDA1541A-S1 chips, and -40V for the differential-input tube amplifier input circuit.
PCU (passive stepped volume controller with bulk metal foil resistors), +5V supply
I just received some high-voltage MOSFETS to tackle the DI4T 200V anode power supply.
Every power supply I modified so far has resulted in stunning improvements in sound quality.
I would have to study the Electron Kinetics Eagle 7A schematics to confirm this, but if it uses a similar method of rejecting mains noise, this may very well contribute to sound quality.
So far I modified following power supplies:
DI4T, +5V digital supply, +5V, -5V and -15V supplies for the TDA1541A-S1 chips, and -40V for the differential-input tube amplifier input circuit.
PCU (passive stepped volume controller with bulk metal foil resistors), +5V supply
I just received some high-voltage MOSFETS to tackle the DI4T 200V anode power supply.
Every power supply I modified so far has resulted in stunning improvements in sound quality.
ALWSR
Hi Ecsdesign
I use this regulator to my Shigaclone CD
maybe you can try it
http://www.at-view.co.uk/alwsr.htm
Hi Ecsdesign
I use this regulator to my Shigaclone CD
maybe you can try it
http://www.at-view.co.uk/alwsr.htm
Attachments
Hi mr whocares,
The direct I2S interface won't work with the existing 4x interpolator / scrambler (48BCK/WS vs 64BCK/WS issue). It also requires a galvanic coupling between both digital audio source and DAC, this causes serious sound quality degradation (similar issues as with conventional power supplies flooding the DAC electronics with HF interference).
When connecting a Toslink optical transmitter (Farnell P/N 1225772) for example, to the esisting SPDIF output on the CDPROII, it can be directly connected to the DAC without any galvanic coupling issues. The CS8416 SPDIF receiver in the DI4MJ or DI4T will produce the required 64BCK/ WS signal. Source jitter is fully blocked by the microcontroller-based tracker .
Please note that the CDPROII may have an integrated pulse transformer for the SPDIF output, so you might look for a suitable (TTL) level signal that's probably present in the pulse transformer drive circuit. This TTL level SPDIF signal can be directly connected to the Toslink optical transmitter input. The Toslink optical transmitter also requires +5V power supply.
thanks for the explanation. i am very looking forward to seeing your complete ready dac (hopefully very soon
currently i am using a cd-pro2m transport which has a i2s output. can i use directly this interface for connecting with your dac or i should build an optical output to be connected to your receiver module?
cdpro2 has a spdif output as well but i can remember you mentioned somewhere that you rather suggest an optical interface than the spdif (coax), correct?
The direct I2S interface won't work with the existing 4x interpolator / scrambler (48BCK/WS vs 64BCK/WS issue). It also requires a galvanic coupling between both digital audio source and DAC, this causes serious sound quality degradation (similar issues as with conventional power supplies flooding the DAC electronics with HF interference).
When connecting a Toslink optical transmitter (Farnell P/N 1225772) for example, to the esisting SPDIF output on the CDPROII, it can be directly connected to the DAC without any galvanic coupling issues. The CS8416 SPDIF receiver in the DI4MJ or DI4T will produce the required 64BCK/ WS signal. Source jitter is fully blocked by the microcontroller-based tracker .
Please note that the CDPROII may have an integrated pulse transformer for the SPDIF output, so you might look for a suitable (TTL) level signal that's probably present in the pulse transformer drive circuit. This TTL level SPDIF signal can be directly connected to the Toslink optical transmitter input. The Toslink optical transmitter also requires +5V power supply.
Hi pocoyo,
The problem introduced by conventional power supplies cannot even be solved by using the world's best hyper-low noise regulator. The problem is the direct galvanic connection between transformer that passes through mains (HF) interference and the load. By doing so, the interference currents also passes the ground routes. This way the interference current is added to the pure DC current of the super regulator, resulting in .... a polluted power supply for the load.
Super low noise regulators are usually tested running on a battery power supply while being placed in a metal box for screening. This already gives a hint about the problems that can be expected when running it on a conventional mains power supply.
So the super regulator is only a part of the solution.
I already experimented with 2nV root Hz regulators, and the problem persisted. The problem was solved when feeding the ultra-low noise regulator by a separate battery power supply, clearly indicating that the problem was caused by the mains power supply NOT the super regulator.
The charge-transfer power supply prevents a direct current loop (that carries all mains interference) between both transformer and load. Now the power is supplied by a "floating" charged capacitor, this is similar than when using a battery power supply. This requires at least two capacitors, the secondary capacitor that continuously feeds the load, and is never being connected to the transformer, and primary capacitor that is disconnected from the secondary capacitor while charging. So both load and transformer are never directly connected, this opens the loop, so interference currents can no longer flow (interrupted loop) and the ground routes stay clean (pure DC).
The problem introduced by conventional power supplies cannot even be solved by using the world's best hyper-low noise regulator. The problem is the direct galvanic connection between transformer that passes through mains (HF) interference and the load. By doing so, the interference currents also passes the ground routes. This way the interference current is added to the pure DC current of the super regulator, resulting in .... a polluted power supply for the load.
Super low noise regulators are usually tested running on a battery power supply while being placed in a metal box for screening. This already gives a hint about the problems that can be expected when running it on a conventional mains power supply.
So the super regulator is only a part of the solution.
I already experimented with 2nV root Hz regulators, and the problem persisted. The problem was solved when feeding the ultra-low noise regulator by a separate battery power supply, clearly indicating that the problem was caused by the mains power supply NOT the super regulator.
The charge-transfer power supply prevents a direct current loop (that carries all mains interference) between both transformer and load. Now the power is supplied by a "floating" charged capacitor, this is similar than when using a battery power supply. This requires at least two capacitors, the secondary capacitor that continuously feeds the load, and is never being connected to the transformer, and primary capacitor that is disconnected from the secondary capacitor while charging. So both load and transformer are never directly connected, this opens the loop, so interference currents can no longer flow (interrupted loop) and the ground routes stay clean (pure DC).