Hi aparatusonitus,
If I am correct, Wadia, Cambridge audio and Trinity use a similar time-domain interpolation method, it's used together with a digital brickwall filter.
The method Wadia uses, enables clocking all DAC chips with an inverted clock signal (data for all DAC chips is now delayed, and changes on the positive going edge of BCK). The result is 4 x linear interpolation in addition to the digital brickwall filter that usually provides 4x or 8x interpolation.
If I am correct, Wadia, Cambridge audio and Trinity use a similar time-domain interpolation method, it's used together with a digital brickwall filter.
The method Wadia uses, enables clocking all DAC chips with an inverted clock signal (data for all DAC chips is now delayed, and changes on the positive going edge of BCK). The result is 4 x linear interpolation in addition to the digital brickwall filter that usually provides 4x or 8x interpolation.
rikkert1978 said:
Yes indeed, I'm looking since weeks if it is finished already.
One more question, since I'm planning do play around with PC and harddisk: is it possible to use the dac via USB, best of course with I2s.
Sorry, I couldn't find some info about it in this giant thread....
BTW, thanks to ECdesigns for all the work, absolutely amazing!
Chapeau!
Juergen
Jump to DI4T?
Hi ECDesigns,
I have received your DI8M modules last October and started to source the components. Indeed I got 8 chips of TDA1541A, but not still not have a good time to solder these modules.
I am interested your threads, especially post #2040. The mainboard getting smaller and will fit to my humble listening room.
Before I decide to start solder these modules, do you think I should wait for your DI4T and jump to this new configuration?
When you release the final DI4T with the new mainboard and SPDIF cleaner?
I hope the modifications of other modules will not too difficult to do.
Thank you.
-ims-
Hi ECDesigns,
I have received your DI8M modules last October and started to source the components. Indeed I got 8 chips of TDA1541A, but not still not have a good time to solder these modules.
I am interested your threads, especially post #2040. The mainboard getting smaller and will fit to my humble listening room.
Before I decide to start solder these modules, do you think I should wait for your DI4T and jump to this new configuration?
When you release the final DI4T with the new mainboard and SPDIF cleaner?
I hope the modifications of other modules will not too difficult to do.
Thank you.
-ims-
Hi jogi,
DI4T has Toslink-only interface to ensure excellent galvanic insulation between source and DAC, preventing ground loops, and picking-up electromagnetic interference through the interlink itself.
However, USB can still be connected, while maintaining excellent galvanic insulation. I sometimes use a small USB to SPDIF converter (PCM2706, bus powered, set to output SPDIF, Toslink transmitter).
At a certain moment I preferred the I2S interface too, but it's a non-standard interface for external DACs, there is the problem of galvanic connection between both source and DAC, and incompatible formats. It's easier to use a standard interface like Toslink, and solve the problems associated with it.
The main problem remains jitter, more specific, jitter spectrum.
I have been testing a new SPDIF cleaner circuit recently.
The idea was reducing jitter amplitude, and neutralizing source jitter spectrum. The test setup contains two cascaded 11.2896 MHz ultra low jitter voltage controlled crystal oscillators.
The first one (SPDIF cleaner circuit) synchronously reclocks the SPDIF signal with an ultra low jitter VCXO crystal oscillator, creating a virtually perfect TTL level SPDIF signal from a jittery source.
The source jitter spectrum is largely substituted by intrinsic VCXO clock jitter spectrum. The discrete VCXOs are specifically designed to produce a relatively neutral jitter spectrum. This should make the DAC more immune to both source jitter amplitude and spectrum.
The second VCXO will further neutralize the jitter spectrum, and and reduce jitter amplitude from the SPDIF cleaner circuit. The second VCXO drives DAC chips, phase comparator, main SPDIF receiver, and WS & DEM clock generation circuit. Multiple Ultra-high speed clock buffers are used, running on a power supply with similar specs as a battery power supply.
I expected to get minor improvements, as the oscillograms showed no measurable difference. Jitter amplitude was already so low that it could no longer be measured with my measuring equipment anyway.
Flipping the switch between "dirty" and the cleaned SPDIF signal made quite an impact. I won't go into details, but the main improvements are resolution, tonal purity and transparence.
DI4T has Toslink-only interface to ensure excellent galvanic insulation between source and DAC, preventing ground loops, and picking-up electromagnetic interference through the interlink itself.
However, USB can still be connected, while maintaining excellent galvanic insulation. I sometimes use a small USB to SPDIF converter (PCM2706, bus powered, set to output SPDIF, Toslink transmitter).
At a certain moment I preferred the I2S interface too, but it's a non-standard interface for external DACs, there is the problem of galvanic connection between both source and DAC, and incompatible formats. It's easier to use a standard interface like Toslink, and solve the problems associated with it.
The main problem remains jitter, more specific, jitter spectrum.
I have been testing a new SPDIF cleaner circuit recently.
The idea was reducing jitter amplitude, and neutralizing source jitter spectrum. The test setup contains two cascaded 11.2896 MHz ultra low jitter voltage controlled crystal oscillators.
The first one (SPDIF cleaner circuit) synchronously reclocks the SPDIF signal with an ultra low jitter VCXO crystal oscillator, creating a virtually perfect TTL level SPDIF signal from a jittery source.
The source jitter spectrum is largely substituted by intrinsic VCXO clock jitter spectrum. The discrete VCXOs are specifically designed to produce a relatively neutral jitter spectrum. This should make the DAC more immune to both source jitter amplitude and spectrum.
The second VCXO will further neutralize the jitter spectrum, and and reduce jitter amplitude from the SPDIF cleaner circuit. The second VCXO drives DAC chips, phase comparator, main SPDIF receiver, and WS & DEM clock generation circuit. Multiple Ultra-high speed clock buffers are used, running on a power supply with similar specs as a battery power supply.
I expected to get minor improvements, as the oscillograms showed no measurable difference. Jitter amplitude was already so low that it could no longer be measured with my measuring equipment anyway.
Flipping the switch between "dirty" and the cleaned SPDIF signal made quite an impact. I won't go into details, but the main improvements are resolution, tonal purity and transparence.
Hi ims,
First of all, DI8M performance is already very high.
However, the DI8M can be further improved to achieve similar performance as the DI4T. Most PCBs used in the DI4T are from the DI8M.
The required modifications of the existing DI8M PCBs are quite easy to carry out.
The only problem is the digital interface & jitter blocking system.
I now plan to design a new (and final) digital interface for both DI8 and DI16. This Toslink interface holds the new twin-VCXO jitter blocking system, and outputs I2S. It can be connected directly to DI8 mainboard or DI16 core PCB. It will probably contain both DIR9001 and CS8416. I have to use CS8416 for the main SPDIF receiver as I need to use slave clock mode, this isn't possible with the DIR9001 (I2S outputs only). The DIR9001 will be used for the SPDIF cleaner circuit.
First of all, DI8M performance is already very high.
However, the DI8M can be further improved to achieve similar performance as the DI4T. Most PCBs used in the DI4T are from the DI8M.
The required modifications of the existing DI8M PCBs are quite easy to carry out.
The only problem is the digital interface & jitter blocking system.
I now plan to design a new (and final) digital interface for both DI8 and DI16. This Toslink interface holds the new twin-VCXO jitter blocking system, and outputs I2S. It can be connected directly to DI8 mainboard or DI16 core PCB. It will probably contain both DIR9001 and CS8416. I have to use CS8416 for the main SPDIF receiver as I need to use slave clock mode, this isn't possible with the DIR9001 (I2S outputs only). The DIR9001 will be used for the SPDIF cleaner circuit.
Hi sandor,
The R1 chip could be a bit problematic, especially in a DI4. Since you already have 2 x S1 grade chips it would be a shame to risk sound quality degradation just by using one chip with higher bit errors (Edl < 2LSB) I would try to swap it for a standard grade chip (Edl < 1 LSB).
I actually use two TDA1541A, and two TDA1541A-S1 chips in my DI4T reference DAC.
The use of higher grade chips is audible when audio set resolution is high enough.
The R1 chip could be a bit problematic, especially in a DI4. Since you already have 2 x S1 grade chips it would be a shame to risk sound quality degradation just by using one chip with higher bit errors (Edl < 2LSB) I would try to swap it for a standard grade chip (Edl < 1 LSB).
I actually use two TDA1541A, and two TDA1541A-S1 chips in my DI4T reference DAC.
The use of higher grade chips is audible when audio set resolution is high enough.
Hi ecdesigns.
Good to see that you have the standalone solution for the Toslink interface finshed. What I'd seen on the scope and listened to - looked quite promising to me some weeks ago. It's outputing I2S right?
I'd really like to try it. It's gonna be interesting how it compares to my USB setup.
Cheers
Klaus
Good to see that you have the standalone solution for the Toslink interface finshed. What I'd seen on the scope and listened to - looked quite promising to me some weeks ago. It's outputing I2S right?
I'd really like to try it. It's gonna be interesting how it compares to my USB setup.
Cheers
Klaus
Yes, I agree with you soundcheck,
Standalone solution for digital interface will get more interesting with this DAC. Now I don't worry to build the complete DI8M anymore thanks to ecdesigns.
Ecdesigns, thanks for doing that modular systems of your DAC. I think now I should start and try to finish my soldering sessions of DI8M and of course try to make it singing. In case the new digital interface available, I will upgrade the DAC for sure. I have already DIR9001 and CS8416 in my drawer and I will keep continue to follow this thread.
Thanks ecdesigns.
-ims-
Standalone solution for digital interface will get more interesting with this DAC. Now I don't worry to build the complete DI8M anymore thanks to ecdesigns.
Ecdesigns, thanks for doing that modular systems of your DAC. I think now I should start and try to finish my soldering sessions of DI8M and of course try to make it singing. In case the new digital interface available, I will upgrade the DAC for sure. I have already DIR9001 and CS8416 in my drawer and I will keep continue to follow this thread.
Thanks ecdesigns.
-ims-
Talking about SPDIF interfaces. Does somebody has on opinion about this one based on Wolfson8804:
http://www.twistedpearaudio.com/docs/wm8804/wm8804_manual.pdf
http://www.wolfsonmicro.com/uploads/documents/en/WM8804_Rev4.0.pdf
Talking about 50ps jitter!?!?
http://www.twistedpearaudio.com/docs/wm8804/wm8804_manual.pdf
http://www.wolfsonmicro.com/uploads/documents/en/WM8804_Rev4.0.pdf
Talking about 50ps jitter!?!?
Hi soundcheck,
The new system is quite different from the one you listened to. The DI4T didn't have the SPDIF cleaner then, and I just completed the twin VCXO system a few days ago. The SPDIF receiver outputs I2S DATA only, it requires external BCK and WS signals that are derived from an ultra low jitter VCXO (SPDIF receiver in slave mode). The SPDIF receiver VCO output (mck / rmck) is used to synchronize the VCXO with the source.
While focussing on jitter amplitude, I should have focussed on jitter spectrum as well. Differences between perceived sound quality, using various digital audio interfaces having similar jitter amplitude might very well be caused by totally different jitter spectra.
Neutralizing jitter spectrum really had an unexpected impact on sound quality. I will try this system with an USB audio interface next.
If the USB interface receiver produces bit-perfect playback, this twin VCXO should have similar impact on sound quality as it had using Toslink or coax.
50ps rms is typical intrinsic VCO clock jitter amplitude, in a practical circuit, timing jitter can easily reach 100ps rms and higher due to (on-chip) ground-bounce, PCB routing, crosstalk with I2S data, power supply quality, and chip tolerances.
The jitter spectrum is also very important.
I am at all not convinced that a chip like DIR1901 (50ps rms typical) or WM8804 (50ps rms typical) could simply solve the source jitter problem.
DI4T timing jitter amplitude should be below 1 / (44,100 * 4) / 2^18 / 2 = 10.8ps rms, in order to achieve full resolution. So both mentioned SPDIF receiver chips alone won't even achieve this basic requirement.
I aim for timing jitter amplitude of below 10.8ps rms, with a neutral (white noise) spectrum, measured directly at each TDA154* BCK input pin.
The new system is quite different from the one you listened to. The DI4T didn't have the SPDIF cleaner then, and I just completed the twin VCXO system a few days ago. The SPDIF receiver outputs I2S DATA only, it requires external BCK and WS signals that are derived from an ultra low jitter VCXO (SPDIF receiver in slave mode). The SPDIF receiver VCO output (mck / rmck) is used to synchronize the VCXO with the source.
While focussing on jitter amplitude, I should have focussed on jitter spectrum as well. Differences between perceived sound quality, using various digital audio interfaces having similar jitter amplitude might very well be caused by totally different jitter spectra.
Neutralizing jitter spectrum really had an unexpected impact on sound quality. I will try this system with an USB audio interface next.
If the USB interface receiver produces bit-perfect playback, this twin VCXO should have similar impact on sound quality as it had using Toslink or coax.
50ps rms is typical intrinsic VCO clock jitter amplitude, in a practical circuit, timing jitter can easily reach 100ps rms and higher due to (on-chip) ground-bounce, PCB routing, crosstalk with I2S data, power supply quality, and chip tolerances.
The jitter spectrum is also very important.
I am at all not convinced that a chip like DIR1901 (50ps rms typical) or WM8804 (50ps rms typical) could simply solve the source jitter problem.
DI4T timing jitter amplitude should be below 1 / (44,100 * 4) / 2^18 / 2 = 10.8ps rms, in order to achieve full resolution. So both mentioned SPDIF receiver chips alone won't even achieve this basic requirement.
I aim for timing jitter amplitude of below 10.8ps rms, with a neutral (white noise) spectrum, measured directly at each TDA154* BCK input pin.
Hi ecdesigns.
Your explanation sounds very promising.
And your value of <=10,8ps sounds to me like a real good job you've done.
The only drawback compared to the Wolfson 8804 solution would be that just one samplerate is supported. But the way I see it - correct me if I am wrong here - Multiple samplerate support means one of your Jitter-Killer
per frequency. Altmann manages this with 3 switchable crystals on the board. ( Nice to have feature to play 96khz master-tracks of course in 16bit only)
The jitter spectrum issue reminds me also at the Charles Altmann solution, where he moves the spectrum to a higher range if I recall it right. This trick
seems to be the reason for the superiority his DAC compared to others ( beside yours of course
)
Cheers
Your explanation sounds very promising.
And your value of <=10,8ps sounds to me like a real good job you've done.
The only drawback compared to the Wolfson 8804 solution would be that just one samplerate is supported. But the way I see it - correct me if I am wrong here - Multiple samplerate support means one of your Jitter-Killer
per frequency. Altmann manages this with 3 switchable crystals on the board. ( Nice to have feature to play 96khz master-tracks of course in 16bit only)
The jitter spectrum issue reminds me also at the Charles Altmann solution, where he moves the spectrum to a higher range if I recall it right. This trick
seems to be the reason for the superiority his DAC compared to others ( beside yours of course
)Cheers
